}
}
+static bool require_zve32f(DisasContext *s)
+{
+ /* RVV + Zve32f = RVV. */
+ if (has_ext(s, RVV)) {
+ return true;
+ }
+
+ /* Zve32f doesn't support FP64. (Section 18.2) */
+ return s->ext_zve32f ? s->sew <= MO_32 : true;
+}
+
static bool require_zve64f(DisasContext *s)
{
/* RVV + Zve64f = RVV. */
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
vext_check_isa_ill(s) &&
/* OPFV instructions ignore vs1 check */
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
require_rvf(s) &&
vext_check_isa_ill(s) &&
vext_check_ms(s, a->rd, a->rs2) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul) &&
+ require_zve32f(s) &&
require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
+ require_zve32f(s) &&
require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
+ require_zve32f(s) &&
require_zve64f(s)) {
gen_set_rm(s, RISCV_FRM_DYN);
{
return slideup_check(s, a) &&
require_rvf(s) &&
+ require_zve32f(s) &&
require_zve64f(s);
}
{
return slidedown_check(s, a) &&
require_rvf(s) &&
+ require_zve32f(s) &&
require_zve64f(s);
}