ARM: dts: imx6sx-sdb: Use new pin names with DCE/DTE for UART pins

Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this
is to distinguish the DCE/DTE functions.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index f6972de..3e5fb72 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -564,17 +564,17 @@
 
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
-                               MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
-                               MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
+                               MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX      0x1b0b1
+                               MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX      0x1b0b1
                        >;
                };
 
                pinctrl_uart5: uart5grp {
                        fsl,pins = <
-                               MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
-                               MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
-                               MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
-                               MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
+                               MX6SX_PAD_KEY_ROW3__UART5_DCE_RX        0x1b0b1
+                               MX6SX_PAD_KEY_COL3__UART5_DCE_TX        0x1b0b1
+                               MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS       0x1b0b1
+                               MX6SX_PAD_KEY_COL2__UART5_DCE_RTS       0x1b0b1
                        >;
                };