mips: Add CPS_NS16550_WIDTH config

On some platforms IO-memory might require to use a proper load/store
instructions (like Baikal-T1 IO-memory). To fix the cps-vec UART debug
printout let's add the CONFIG_CPS_NS16550_WIDTH config to determine which
instructions lb/sb, lh/sh or lw/sw are required for MMIO operations.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 93a2974..7a8d94c 100644 (file)
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -148,4 +148,14 @@ config MIPS_CPS_NS16550_SHIFT
          form their addresses. That is, log base 2 of the span between
          adjacent ns16550 registers in the system.
 
+config MIPS_CPS_NS16550_WIDTH
+       int "UART Register Width"
+       default 1
+       help
+         ns16550 registers width. UART registers IO access methods will be
+         selected in accordance with this parameter. By setting it to 1, 2 or
+         4 UART registers will be accessed by means of lb/sb, lh/sh or lw/sw
+         instructions respectively. Any value not from that set activates
+         lb/sb instructions.
+
 endif # MIPS_CPS_NS16550_BOOL

diff --git a/arch/mips/kernel/cps-vec-ns16550.S b/arch/mips/kernel/cps-vec-ns16550.S
index d5a67b4..30725e1 100644 (file)
--- a/arch/mips/kernel/cps-vec-ns16550.S
+++ b/arch/mips/kernel/cps-vec-ns16550.S
@@ -14,16 +14,30 @@
 #define UART_TX_OFS    (UART_TX << CONFIG_MIPS_CPS_NS16550_SHIFT)
 #define UART_LSR_OFS   (UART_LSR << CONFIG_MIPS_CPS_NS16550_SHIFT)
 
+#if CONFIG_MIPS_CPS_NS16550_WIDTH == 1
+# define UART_L                lb
+# define UART_S                sb
+#elif CONFIG_MIPS_CPS_NS16550_WIDTH == 2
+# define UART_L                lh
+# define UART_S                sh
+#elif CONFIG_MIPS_CPS_NS16550_WIDTH == 4
+# define UART_L                lw
+# define UART_S                sw
+#else
+# define UART_L                lb
+# define UART_S                sb
+#endif
+
 /**
  * _mips_cps_putc() - write a character to the UART
  * @a0: ASCII character to write
  * @t9: UART base address
  */
 LEAF(_mips_cps_putc)
-1:     lw              t0, UART_LSR_OFS(t9)
+1:     UART_L          t0, UART_LSR_OFS(t9)
        andi            t0, t0, UART_LSR_TEMT
        beqz            t0, 1b
-       sb              a0, UART_TX_OFS(t9)
+       UART_S          a0, UART_TX_OFS(t9)
        jr              ra
        END(_mips_cps_putc)