case FM7_MAINIO_OPNPORTB_CHANGED:
opnport_a = data & mask;
break;
+ case FM7_MAINIO_PSG_IRQ:
+ break;
+ case FM7_MAINIO_OPN_IRQ:
+ intstat_opn = val_b;
+ do_irq(val_b);
+ break;
+ case FM7_MAINIO_WHG_IRQ:
+ intstat_whg = val_b;
+ do_irq(val_b);
+ break;
+ case FM7_MAINIO_THG_IRQ:
+ intstat_thg = val_b;
+ do_irq(val_b);
+ break;
case FM7_MAINIO_FDC_DRQ:
fdc_drq = val_b;
if(fdc_drq) {
}
-uint32 FM7_MAINIO::read_memory_mapped_io8(uint32 addr)
+uint32 FM7_MAINIO::read_data8(uint32 addr)
{
addr = addr & 0xff; //
return 0xff;
}
-void FM7_MAINIO::write_memory_mapped_io8(uint32 addr, uint32 data)
+void FM7_MAINIO::write_data8(uint32 addr, uint32 data)
{
this->wait();
keyboard->set_context_mainio(mainio);
keyboard->set_context_subio(subio);
- //keyboard->set_context_interrupt(mainio, SIG_FM7_MAIN_KEYIRQ, 0x0080);
- //keyboard->set_context_interrupt(subio, SIG_FM7_SUB_KEYFIRQ, 0x0080);
mainmem->set_context_submem(submem);
// mainmem->set_context_cpu(maincpu);
mainio->set_context_maincpu(maincpu);
- mainio->set_context_subcpu(subcpu);
+ mainio->set_context_subio(subio);
- subio->set_context_maincpu(maincpu);
+ subio->set_context_mainio(mainio);
subio->set_context_subcpu(subcpu);
// Palette, VSYNC, HSYNC, Multi-page, display mode.
display->set_context_subcpu(subcpu); // For VRAM?
- fdc->set_context_irq(mainio, SIG_FM7_FDC_IRQ, 0xffffffff);
- fdc->set_context_drq(mainio, SIG_FM7_FDC_DRQ, 0xffffffff);
+ fdc->set_context_irq(mainio, FM7_MAINIO_FDC_IRQ, 0xffffffff);
+ fdc->set_context_drq(mainio, FM7_MAINIO_FDC_DRQ, 0xffffffff);
- psg->set_context_irq(mainio, SIG_FM7_PSG_IRQ, 0xffffffff);
- opn[0]->set_context_irq(mainio, SIG_FM7_OPN_IRQ, 0xffffffff);
- opn[1]->set_context_irq(mainio, SIG_FM7_WHG_IRQ, 0xffffffff);
- opn[2]->set_context_irq(mainio, SIG_FM7_THG_IRQ, 0xffffffff);
+ psg->set_context_irq(mainio, FM7_MAINIO_PSG_IRQ, 0xffffffff);
+ opn[0]->set_context_irq(mainio, FM7_MAINIO_OPN_IRQ, 0xffffffff);
+ opn[1]->set_context_irq(mainio, FM7_MAINIO_WHG_IRQ, 0xffffffff);
+ opn[2]->set_context_irq(mainio, FM7_MAINIO_THG_IRQ, 0xffffffff);
opn[0]->set_context_port_a(mainio, SIG_FM7_OPN_JOY_A, 0xff);
opn[0]->set_context_port_b(mainio, SIG_FM7_OPN_JOY_B, 0xff);
FM7_MAINIO_SUB_ATTENTION, // FIRQ
FM7_MAINIO_EXTDET,
FM7_MAINIO_BEEP, // BEEP From sub
+ FM7_MAINIO_PSG_IRQ,
+ FM7_MAINIO_OPN_IRQ,
+ FM7_MAINIO_WHG_IRQ,
+ FM7_MAINIO_THG_IRQ,
FM7_MAINIO_OPNPORTA_CHANGED, // Joystick
FM7_MAINIO_OPNPORTB_CHANGED, // Joystick
FM7_MAINIO_FDC_DRQ,
bool irqmask_keyboard; // bit0: "0" = mask.
/* FD03: R */
- uint8 irqstat_reg0 = 0xff; // bit 3-0, '0' is happened, '1' is not happened.
+ uint8 irqstat_reg0; // bit 3-0, '0' is happened, '1' is not happened.
// bit3 : extended interrupt
// bit2-0: Same as FD02 : W .
/* FD03 : W , '1' = ON*/
bool extdet_neg; // bit0 : '1' = none , '0' = exists.
/* FD05 : W */
bool sub_haltreq; // bit7 : '1' = HALT, maybe dummy.
- bool sub_cansel; // bit6 : '1' Cansel req.
+ bool sub_cancel; // bit6 : '1' Cancel req.
bool z80_sel; // bit0 : '1' = Z80. Maybe only FM-7/77.
/* FD06 : R/W : RS-232C */
KANJIROM *kanjiclass1;
DISPLAY *display;
MC6809 *maincpu;
- MC6809 *subcpu;
+ DEVICE *mainmem;
+ DEVICE *subio;
Z80 *z80;
public:
FM7_MAINIO(VM* parent_vm, EMU* parent_emu) : MEMORY(parent_vm, parent_emu)
sub_busy = false;
extdet_neg = false;
sub_haltreq = false;
- sub_cansel = false; // bit6 : '1' Cansel req.
+ sub_cancel = false; // bit6 : '1' Cancel req.
z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
// FD06,07
intstat_syndet = false;
uint8 get_fdc_data(void);
- virtual void write_memory_mapped_io8(uint32 addr, uint32 data);
- virtual uint32 read_memory_mapped_io8(uint32 addr);
+ virtual void write_data8(uint32 addr, uint32 data);
+ virtual uint32 read_data8(uint32 addr);
void write_signals(int id, uint32 data, uint32 mask);
void set_context_kanjirom_class1(KANJIROM *p)
void set_context_maincpu(MC6809 *p){
maincpu = p;
}
- void set_context_subcpu(MC6809 *p){
- subcpu = p;
+ void set_context_mainmem(DEVICE *p){
+ mainmem = p;
+ }
+ void set_context_subio(DEVICE *p){
+ subio = p;
}
void set_context_z80cpu(Z80 *p){
z80 = p;
*realaddr = addr - 0xfd00;
return FM7_MAINMEM_MMIO;
}
- if(addr < 0xfff0) {
+ if(addr < 0xffe0) {
if(addr < 0xffe0) mainio->wait();
*realaddr = addr - 0xfe00;
//if(mainio->get_boot_romram() != true) return FM7_MAINMEM_BOOTROM_RAM;
}
}
if(addr < 0xfffe) {
- *realaddr = addr - 0xfff0;
+ *realaddr = addr - 0xffe0;
return FM7_MAINMEM_VECTOR;
}
if(addr < 0x10000) {
bank = getbank(addr, &realaddr);
if(bank < 0) return 0xff; // Illegal
-
+
+ if(bank == FM7_MAINMEM_SHAREDRAM) {
+ if(submem->read_signal(SIG_SUBCPU_HALT) != 0) return 0xff; // Not halt
+ return submem->read_data8(realaddr + 0xd000); // Okay?
+ }
if(read_table[bank].dev != NULL) {
- return read_table[bank].dev->read_memory_mapped_io8(realaddr);
+ return read_table[bank].dev->read_data8(realaddr);
} else {
if(read_table[bank].memory != NULL) {
return read_table[bank].memory[realaddr];
bank = getbank(addr, &realaddr);
if(bank < 0) return; // Illegal
+ if(bank == FM7_MAINMEM_SHAREDRAM) {
+ if(submem->read_signal(SIG_SUBCPU_HALT) != 0) return; // Not halt
+ submem->write_data8(realaddr + 0xd000, data); // Okay?
+ return;
+ }
if(write_table[bank].dev != NULL) {
- write_table[bank].dev->write_memory_mapped_io8(realaddr, data);
+ write_table[bank].dev->write_data8(realaddr, data);
} else {
if(write_table[bank].memory != NULL) {
write_table[bank].memory[realaddr] = (uint8)(data & 0x000000ff);
if(fm7_bootroms[i] != NULL) free(fm7_bootroms[i]);
fm7_bootroms[i] = NULL;
}
+ delete mainio;
}
-void FM7_MAINMEM::initialize()
+void FM7_MAINMEM::initialize(void)
{
int i;
// Initialize table
write_table[i].memory = NULL;
i = FM7_MAINMEM_MMIO;
- read_table[i].dev = fm7_io_main;
+ mainio = new FM7_MAINIO();
+ read_table[i].dev = mainio;
read_table[i].memory = NULL;
- write_table[i].dev = fm7_io_main;
+ write_table[i].dev = mainio;
write_table[i].memory = NULL;
for(i = FM7_MAINMEM_BOOTROM_BAS; i <= FM7_MAINMEM_BOOTROM_RAM; i++) {
write_table[FM7_BAINMEM_BOOTROM_RAM].memory = read_table[FM7_BAINMEM_BOOTROM_RAM].memory; // Write enabled on BOOTRAM.
i = FM7_MAINMEM_VECTOR;
- memset(fm7_mainmem_bootrom_vector, 0x00, 0x0e);
+ memset(fm7_mainmem_bootrom_vector, 0x00, 0x1e);
read_table[i].dev = NULL;
read_table[i].memory = fm7_mainmem_bootrom_vector;
write_table[i].dev = NULL;
class DEVICE;
class MEMORY;
-class FM7_SHAREDRAM;
-class FM7_MAIN_IO;
-class FM7_DIPSW;
-
+class FM7_MAINIO;
class FM7_MAINMEM : public MEMORY
{
-
protected:
- EMU *p_emu;
- VM *p_vm;
+ EMU *p_emu;
+ VM *p_vm;
- uint8 fm7_mainmem_omote[0x8000];
- uint8 fm7_mainmem_ura[0x7c00];
- uint8 fm7_mainmem_basicrom[0x7c00];
- uint8 fm7_mainmem_bioswork[0x80];
- uint8 *fm7_bootroms[4];
- uint8 fm7_mainmem_bootrom_vector[0x0e]; // Without
- uint8 fm7_mainmem_resetvector[2] = {0xfe, 0x00}; // Reset vector. Addr = 0xfe00.
+ uint8 fm7_mainmem_omote[0x8000];
+ uint8 fm7_mainmem_ura[0x7c00];
+ uint8 fm7_mainmem_basicrom[0x7c00];
+ uint8 fm7_mainmem_bioswork[0x80];
+ uint8 *fm7_bootroms[4];
+ uint8 fm7_mainmem_bootrom_vector[0x1e]; // Without
+ uint8 fm7_mainmem_resetvector[2] = {0xfe, 0x00}; // Reset vector. Addr = 0xfe00.
- bool diag_load_basicrom = false;
- bool diag_load_bootrom_bas = false;
- bool diag_load_bootrom_dos = false;
-
- virtual int getbank(uint32 addr, uint32 *realaddr);
+ bool diag_load_basicrom = false;
+ bool diag_load_bootrom_bas = false;
+ bool diag_load_bootrom_dos = false;
+
+ virtual int getbank(uint32 addr, uint32 *realaddr);
+ FM7_MAINIO *mainio;
+ DEVICE *submem;
public:
- FM7_MAINMEM(VM* parent_vm, EMU* parent_emu);
- ~FM7_MAINMEM();
- virtual uint32 read_data8(uint32 addr);
- virtual void write_data8(uint32 addr, uint32 data);
- virtual uint32 read_data16(uint32 addr);
- virtual void write_data16(uint32 addr, uint32 data);
- virtual uint32 read_data32(uint32 addr);
- virtual void write_data32(uint32 addr, uint32 data);
- bool get_loadstat_basicrom(void){
- return diag_load_basicrom;
- }
- bool get_loadstat_bootrom_bas(void){
- return diag_load_bootrom_bas;
- }
- bool get_loadstat_bootrom_dos(void){
- return diag_load_bootrom_dos;
- }
-}
+ FM7_MAINMEM(VM* parent_vm, EMU* parent_emu);
+ ~FM7_MAINMEM();
+ virtual uint32 read_data8(uint32 addr);
+ virtual void write_data8(uint32 addr, uint32 data);
+ virtual uint32 read_data16(uint32 addr);
+ virtual void write_data16(uint32 addr, uint32 data);
+ virtual uint32 read_data32(uint32 addr);
+ virtual void write_data32(uint32 addr, uint32 data);
+ void initialize(void);
+
+ bool get_loadstat_basicrom(void){
+ return diag_load_basicrom;
+ }
+ bool get_loadstat_bootrom_bas(void){
+ return diag_load_bootrom_bas;
+ }
+ bool get_loadstat_bootrom_dos(void){
+ return diag_load_bootrom_dos;
+ }
+ void set_context_submem(DEVICE *p){
+ submem = p;
+ }
+};
#endif