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ARM: dts: msm: Update GPU bus IB votes for SDM660
authorMihir Patel <mihirp@codeaurora.org>
Fri, 6 Jan 2017 08:59:17 +0000 (14:29 +0530)
committerMihir Patel <mihirp@codeaurora.org>
Fri, 20 Jan 2017 09:04:54 +0000 (14:34 +0530)
A512 GPU clock plan is revised hence need to adjust IB
bus votes for respective GPU power levels. Update GPU
bus votes as per new GPU clock plan for SDM660.
Also adjust GPU IB votes as per dual channel DDR
recommendation.

Change-Id: Ia68bd5dee8bf9d037510877c647c5c3a74bdce99
Signed-off-by: Mihir Patel <mihirp@codeaurora.org>
arch/arm/boot/dts/qcom/sdm660-gpu.dtsi

index d347f03..1e62a24 100644 (file)
                 * subsystem is inactive
                 */
                qcom,active-only;
+               /*
+                * IB votes in MBPS, derived using below formula
+                * IB = (DDR frequency * DDR bus width in Bytes * Dual rate)
+                * Note: IB vote is per DDR channel vote
+                */
                qcom,bw-tbl =
                        <     0 /*  off     */ >,
-                       <   762 /*  100 MHz */ >,
-                       <  1144 /*  150 MHz */ >,
-                       <  1525 /*  200 MHz */ >,
-                       <  2288 /*  300 MHz */ >,
-                       <  3143 /*  412 MHz */ >,
-                       <  4173 /*  547 MHz */ >,
-                       <  5195 /*  681 MHz */ >,
-                       <  5859 /*  768 MHz */ >,
-                       <  7759 /*  1017 MHz */ >,
-                       <  9887 /*  1296 MHz */ >,
-                       <  10327 /*  1353 MHz */ >,
-                       <  11863 /*  1555 MHz */ >,
-                       <  13763 /*  1804 MHz */ >;
+                       <   381 /*  100 MHz */ >,
+                       <   572 /*  150 MHz */ >,
+                       <   762 /*  200 MHz */ >,
+                       <  1144 /*  300 MHz */ >,
+                       <  1571 /*  412 MHz */ >,
+                       <  2086 /*  547 MHz */ >,
+                       <  2597 /*  681 MHz */ >,
+                       <  2929 /*  768 MHz */ >,
+                       <  3879 /*  1017 MHz */ >,
+                       <  4943 /*  1296 MHz */ >,
+                       <  5161 /*  1353 MHz */ >,
+                       <  5931 /*  1555 MHz */ >,
+                       <  6881 /*  1804 MHz */ >;
        };
 
        msm_gpu: qcom,kgsl-3d0@5000000 {
                /* Bus Scale Settings */
                qcom,gpubw-dev = <&gpubw>;
                qcom,bus-control;
-               qcom,bus-width = <16>;
+               /* GPU to BIMC bus width, VBIF data transfer in 1 cycle */
+               qcom,bus-width = <32>;
                qcom,msm-bus,name = "grp3d";
                qcom,msm-bus,num-cases = <14>;
                qcom,msm-bus,num-paths = <1>;
                qcom,msm-bus,vectors-KBps =
                                <26 512 0 0>,
 
-                               <26 512 0 800000>,      /*  1 bus=100  */
-                               <26 512 0 1200000>,     /*  2 bus=150  */
-                               <26 512 0 1600000>,     /*  3 bus=200  */
-                               <26 512 0 2400000>,     /*  4 bus=300  */
-                               <26 512 0 3296000>,     /*  5 bus=412  */
-                               <26 512 0 4376000>,     /*  6 bus=547  */
-                               <26 512 0 5448000>,     /*  7 bus=681  */
-                               <26 512 0 6144000>,     /*  8 bus=768  */
-                               <26 512 0 8136000>,     /*  9 bus=1017 */
-                               <26 512 0 10368000>,    /* 10 bus=1296 */
-                               <26 512 0 10824000>,    /* 11 bus=1353 */
-                               <26 512 0 12440000>,    /* 12 bus=1555 */
-                               <26 512 0 14432000>;    /* 13 bus=1804 */
+                               <26 512 0 400000>,     /*  1 bus=100  */
+                               <26 512 0 600000>,     /*  2 bus=150  */
+                               <26 512 0 800000>,     /*  3 bus=200  */
+                               <26 512 0 1200000>,    /*  4 bus=300  */
+                               <26 512 0 1648000>,    /*  5 bus=412  */
+                               <26 512 0 2188000>,    /*  6 bus=547  */
+                               <26 512 0 2724000>,    /*  7 bus=681  */
+                               <26 512 0 3072000>,    /*  8 bus=768  */
+                               <26 512 0 4068000>,    /*  9 bus=1017 */
+                               <26 512 0 5184000>,    /* 10 bus=1296 */
+                               <26 512 0 5412000>,    /* 11 bus=1353 */
+                               <26 512 0 6220000>,    /* 12 bus=1555 */
+                               <26 512 0 7216000>;    /* 13 bus=1804 */
 
                /* GDSC regulator names */
                regulator-names = "vddcx", "vdd";
                        qcom,gpu-pwrlevel@0 {
                                reg = <0>;
                                qcom,gpu-freq = <750000000>;
-                               qcom,bus-freq = <12>;
-                               qcom,bus-min = <11>;
+                               qcom,bus-freq = <13>;
+                               qcom,bus-min = <12>;
                                qcom,bus-max = <13>;
                        };
 
                                reg = <1>;
                                qcom,gpu-freq = <700000000>;
                                qcom,bus-freq = <11>;
-                               qcom,bus-min = <10>;
+                               qcom,bus-min = <11>;
                                qcom,bus-max = <13>;
                        };
 
                        qcom,gpu-pwrlevel@2 {
                                reg = <2>;
                                qcom,gpu-freq = <647000000>;
-                               qcom,bus-freq = <10>;
+                               qcom,bus-freq = <11>;
                                qcom,bus-min = <10>;
                                qcom,bus-max = <12>;
                        };
                        qcom,gpu-pwrlevel@3 {
                                reg = <3>;
                                qcom,gpu-freq = <588000000>;
-                               qcom,bus-freq = <9>;
+                               qcom,bus-freq = <10>;
                                qcom,bus-min = <9>;
-                               qcom,bus-max = <11>;
+                               qcom,bus-max = <12>;
                        };
 
                        /* SVS_L1 */
                                reg = <4>;
                                qcom,gpu-freq = <465000000>;
                                qcom,bus-freq = <9>;
-                               qcom,bus-min = <7>;
+                               qcom,bus-min = <8>;
                                qcom,bus-max = <11>;
                        };
 
                        qcom,gpu-pwrlevel@5 {
                                reg = <5>;
                                qcom,gpu-freq = <370000000>;
-                               qcom,bus-freq = <7>;
-                               qcom,bus-min = <5>;
+                               qcom,bus-freq = <8>;
+                               qcom,bus-min = <6>;
                                qcom,bus-max = <9>;
                        };
 
                                reg = <7>;
                                qcom,gpu-freq = <160000000>;
                                qcom,bus-freq = <3>;
-                               qcom,bus-min = <2>;
+                               qcom,bus-min = <3>;
                                qcom,bus-max = <5>;
                        };