SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0);
smc->legacy_irq_allocation = true;
+ smc->irq = &spapr_irq_xics_legacy;
}
DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
ics_pic_print_info(spapr->ics, mon);
}
-#define SPAPR_IRQ_XICS_NR_IRQS 0x400
+#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
#define SPAPR_IRQ_XICS_NR_MSIS \
(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
return first + ics->offset;
}
+
+#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
+
+sPAPRIrq spapr_irq_xics_legacy = {
+ .nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
+ .nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
+
+ .init = spapr_irq_init_xics,
+ .claim = spapr_irq_claim_xics,
+ .free = spapr_irq_free_xics,
+ .qirq = spapr_qirq_xics,
+ .print_info = spapr_irq_print_info_xics,
+};
} sPAPRIrq;
extern sPAPRIrq spapr_irq_xics;
+extern sPAPRIrq spapr_irq_xics_legacy;
int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);