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Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.
author
Johnny Chen
<johnny.chen@apple.com>
Mon, 25 Jan 2010 22:54:29 +0000
(22:54 +0000)
committer
Johnny Chen
<johnny.chen@apple.com>
Mon, 25 Jan 2010 22:54:29 +0000
(22:54 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMRegisterInfo.td
patch
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diff --git
a/lib/Target/ARM/ARMRegisterInfo.td
b/lib/Target/ARM/ARMRegisterInfo.td
index
e4b1808
..
0d4200c
100644
(file)
--- a/
lib/Target/ARM/ARMRegisterInfo.td
+++ b/
lib/Target/ARM/ARMRegisterInfo.td
@@
-124,7
+124,7
@@
def FPSCR : ARMReg<1, "fpscr">;
//
def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
R7, R8, R9, R10, R11, R12,
-
LR, SP
, PC]> {
+
SP, LR
, PC]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;