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clk: imx: scu: bypass cpu clock save and restore
authorDong Aisheng <aisheng.dong@nxp.com>
Fri, 4 Jun 2021 09:09:36 +0000 (17:09 +0800)
committerAbel Vesa <abel.vesa@nxp.com>
Mon, 14 Jun 2021 09:34:19 +0000 (12:34 +0300)
CPU clock is managed by ATF. No need save and restore.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
drivers/clk/imx/clk-scu.c

index 680b265..d87a1a1 100644 (file)
@@ -538,6 +538,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
 static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
 {
        struct clk_scu *clk = dev_get_drvdata(dev);
+       u32 rsrc_id = clk->rsrc_id;
+
+       if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
+           (rsrc_id == IMX_SC_R_A72))
+               return 0;
 
        clk->rate = clk_hw_get_rate(&clk->hw);
        clk->is_enabled = clk_hw_is_enabled(&clk->hw);
@@ -554,8 +559,13 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
 static int __maybe_unused imx_clk_scu_resume(struct device *dev)
 {
        struct clk_scu *clk = dev_get_drvdata(dev);
+       u32 rsrc_id = clk->rsrc_id;
        int ret = 0;
 
+       if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
+           (rsrc_id == IMX_SC_R_A72))
+               return 0;
+
        if (clk->rate) {
                ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
                dev_dbg(dev, "restore rate %d %s\n", clk->rate,