Using deinterlaced chroma in DNDI kernel

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
index 90089ac..280d37a 100644 (file)
--- a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
+++ b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
@@ -89,19 +89,14 @@ SAVE_DN_CURR:
     mov (8)     mudMSGHDR_DN(0)<1>     rMSGSRC.0<8;8,1>:ud
     send (8)    dNULLREG    mMSGHDR_DN   udDUMMY_NULL    nDATAPORT_WRITE    nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud
 
-
-/////////////////////////////NV12 UV Copy 422/////////////////////////////////////////////////////
-               //Read UV through DATAPORT    
-    add  (2) rMSGSRC.0<1>:d     wORIX<2;2,1>:w    wSRC_H_ORI_OFFSET<2;2,1>:w       // Source Y Block origin
-    asr (1)  rMSGSRC.1<1>:d     rMSGSRC.1<0;1,0>:d       1:w   // U/V block origin should be half of Y's
-    mov (1)  rMSGSRC.2<1>:ud    nDPR_BLOCK_SIZE_UV:ud          // U/V block width and height (16x2)
-    mov  (8) mudMSGHDR_DN<1>     rMSGSRC<8;8,1>:ud
-    send (8) udBOT_U_IO(0)<1>     mMSGHDR_DN    udDUMMY_NULL    nDATAPORT_READ    nDPMR_MSGDSC+nRESLEN_1+nBI_CURRENT_SRC_UV:ud
-
                //Write UV through DATAPORT
                mov (2)     rMSGSRC.0<1>:ud        wORIX<2;2,1>:w               // X origin and Y origin
                asr (1)     rMSGSRC.1<1>:d         rMSGSRC.1<0;1,0>:d    1:w  // U/V block origin should be half of Y's
     mov (1)     rMSGSRC.2<1>:ud        nDPR_BLOCK_SIZE_UV:ud        // block width and height (16x2)
     mov (8)     mudMSGHDR_DN(0)<1>     rMSGSRC.0<8;8,1>:ud
-    mov (8)                    mudMSGHDR_DN(1)<1>               udBOT_U_IO(0)<8;8,1>
+
+    mov (8) mubMSGHDR_DN(1, 0)<2>      ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 1)<16 ;8,2>
+    mov (8) mubMSGHDR_DN(1, 1)<2>      ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 16)<16 ;8,2>        
+    mov (8) mubMSGHDR_DN(1, 16)<2>      ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2>
+    mov (8) mubMSGHDR_DN(1, 17)<2>      ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2>        
     send (8)    dNULLREG    mMSGHDR_DN   udDUMMY_NULL    nDATAPORT_WRITE    nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:ud 
\ No newline at end of file

diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
index aee45d1..38050f7 100644 (file)
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
@@ -64,25 +64,23 @@
    { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
    { 0x01600031, 0x20000c04, 0x508d0000, 0x06082007 },
-   { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 },
-   { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
-   { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
-   { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
-   { 0x01600031, 0x28000c01, 0x408d0000, 0x0218a002 },
    { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
    { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
    { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
-   { 0x00600001, 0x20400022, 0x008d0800, 0x00000000 },
+   { 0x00600001, 0x40400232, 0x00ae0501, 0x00000000 },
+   { 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 },
+   { 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 },
+   { 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 },
    { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 },
    { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff },
    { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
    { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
    { 0x00010220, 0x34001c00, 0x00001400, 0x00000008 },
-   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff68 },
+   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff6c },
    { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
    { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
-   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff62 },
+   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff66 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
    { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 },

diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
index 29003af..6b56ac6 100644 (file)
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
@@ -137,25 +137,23 @@
    { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
    { 0x05600031, 0x20000cc4, 0x00000020, 0x06094007 },
-   { 0x00200040, 0x210035a5, 0x004500a0, 0x00450074 },
-   { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
-   { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
-   { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
-   { 0x04600031, 0x28000cc1, 0x00000020, 0x02198002 },
    { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
    { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
    { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
-   { 0x00600001, 0x20400022, 0x008d0800, 0x00000000 },
+   { 0x00600001, 0x40400232, 0x00ae0501, 0x00000000 },
+   { 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 },
+   { 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 },
+   { 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 },
    { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 },
    { 0x01000040, 0x20863dad, 0x00000086, 0xffffffff },
    { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
    { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
    { 0x00010220, 0x34001c00, 0x00001400, 0x00000008 },
-   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff68 },
+   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff6c },
    { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
    { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
-   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff62 },
+   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff66 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
    { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 },