drm/i915: Fix SEL_FETCH_PLANE_*(PIPE_B+) register addresses

Fix typo in the _SEL_FETCH_PLANE_BASE_1_B register base address.

Fixes: a5523e2ff074a5 ("drm/i915: Add PSR2 selective fetch registers")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/5400
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: <stable@vger.kernel.org> # v5.9+
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220421162221.2261895-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa0062d..c997bd6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5161,7 +5161,7 @@
 #define _SEL_FETCH_PLANE_BASE_6_A              0x70940
 #define _SEL_FETCH_PLANE_BASE_7_A              0x70960
 #define _SEL_FETCH_PLANE_BASE_CUR_A            0x70880
-#define _SEL_FETCH_PLANE_BASE_1_B              0x70990
+#define _SEL_FETCH_PLANE_BASE_1_B              0x71890
 
 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
                                             _SEL_FETCH_PLANE_BASE_1_A, \