.displayrtids = 256,
};
+static const struct intel_sa_info rkl_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 20, /* GB/s */
+ .displayrtids = 128,
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_GEN(dev_priv, 12))
+ if (IS_ROCKETLAKE(dev_priv))
+ icl_get_bw_info(dev_priv, &rkl_sa_info);
+ else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, &tgl_sa_info);
else if (IS_GEN(dev_priv, 11))
icl_get_bw_info(dev_priv, &icl_sa_info);