OSDN Git Service

drm/i915: Move dbuf slice update to proper place
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Sun, 2 Feb 2020 23:06:26 +0000 (01:06 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 5 Feb 2020 17:13:53 +0000 (19:13 +0200)
Current DBuf slices update wasn't done in proper
place, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.

v2: Fix to use dev_priv and intel_atomic_state
    instead of skl_ddb_values
    (to be nuked in Villes patch)

v3: Renamed "enabled_slices" to "enabled_dbuf_slices_num"
    (Matt Roper)

v4: - Rebase against drm-tip.
    - Move post_update closer to optimize_watermarks,
      to prevent unneeded noise from underrun reporting
      (Ville Syrjälä)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200202230630.8975-3-stanislav.lisovskiy@intel.com
drivers/gpu/drm/i915/display/intel_display.c

index 2e78a9b..afb56a9 100644 (file)
@@ -15445,13 +15445,33 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
                                       state);
 }
 
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+       struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+       u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
+       u8 required_slices = state->enabled_dbuf_slices_num;
+
+       /* If 2nd DBuf slice required, enable it here */
+       if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+               icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+       struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+       u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
+       u8 required_slices = state->enabled_dbuf_slices_num;
+
+       /* If 2nd DBuf slice is no more required disable it */
+       if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+               icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 {
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        struct intel_crtc *crtc;
        struct intel_crtc_state *old_crtc_state, *new_crtc_state;
-       u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
-       u8 required_slices = state->enabled_dbuf_slices_num;
        struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
        const u8 num_pipes = INTEL_NUM_PIPES(dev_priv);
        u8 update_pipes = 0, modeset_pipes = 0;
@@ -15472,10 +15492,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
                }
        }
 
-       /* If 2nd DBuf slice required, enable it here */
-       if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
-               icl_dbuf_slices_update(dev_priv, required_slices);
-
        /*
         * Whenever the number of active pipes changes, we need to make sure we
         * update the pipes in the right order so that their ddb allocations
@@ -15577,9 +15593,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 
        WARN_ON(modeset_pipes);
 
-       /* If 2nd DBuf slice is no more required disable it */
-       if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
-               icl_dbuf_slices_update(dev_priv, required_slices);
 }
 
 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -15706,6 +15719,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
        if (state->modeset)
                intel_encoders_update_prepare(state);
 
+       /* Enable all new slices, we might need */
+       icl_dbuf_slice_pre_update(state);
+
        /* Now enable the clocks, plane, pipe, and connectors that we set up. */
        dev_priv->display.commit_modeset_enables(state);
 
@@ -15759,6 +15775,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
                        dev_priv->display.optimize_watermarks(state, crtc);
        }
 
+       /* Disable all slices, we don't need */
+       icl_dbuf_slice_post_update(state);
+
        for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
                intel_post_plane_update(state, crtc);