[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX

The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.

Patch by Qing Shan Zhang (steven.zhang).

Differential Revision: https://reviews.llvm.org/D47178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333150 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td
index 71f2134..85eb6e8 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/lib/Target/PowerPC/PPCInstrVSX.td
@@ -129,7 +129,7 @@ let Uses = [RM] in {
     def LXSDX : XX1Form_memOp<31, 588,
                         (outs vsfrc:$XT), (ins memrr:$src),
                         "lxsdx $XT, $src", IIC_LdStLFD,
-                        [(set f64:$XT, (load xoaddr:$src))]>;
+                        []>;
 
     // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
     let isPseudo = 1, CodeSize = 3 in
@@ -160,7 +160,7 @@ let Uses = [RM] in {
     def STXSDX : XX1Form_memOp<31, 716,
                         (outs), (ins vsfrc:$XT, memrr:$dst),
                         "stxsdx $XT, $dst", IIC_LdStSTFD,
-                        [(store f64:$XT, xoaddr:$dst)]>;
+                        []>;
 
     // Pseudo instruction XFSTOREf64  will be expanded to STXSDX or STFDX later
     let isPseudo = 1, CodeSize = 3 in

diff --git a/test/CodeGen/PowerPC/bitcasts-direct-move.ll b/test/CodeGen/PowerPC/bitcasts-direct-move.ll
index d6c7dd3..e5fd9f5 100644 (file)
--- a/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ b/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -18,7 +18,7 @@ define i64 @f64toi64(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
-; CHECK-P7: stxsdx 1,
+; CHECK-P7: stfdx 1,
 ; CHECK-P7: ld 3,
 ; CHECK: mffprd 3, 1
 }
@@ -39,7 +39,7 @@ entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
-; CHECK-P7: lxsdx 1,
+; CHECK-P7: lfdx 1,
 ; CHECK: mtvsrd 1, 3
 }
 
@@ -58,7 +58,7 @@ define i64 @f64toi64u(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
-; CHECK-P7: stxsdx 1,
+; CHECK-P7: stfdx 1,
 ; CHECK-P7: ld 3,
 ; CHECK: mffprd 3, 1
 }
@@ -79,6 +79,6 @@ entry:
   %0 = bitcast i64 %a to double
   ret double %0
 ; CHECK-P7: std 3,
-; CHECK-P7: lxsdx 1,
+; CHECK-P7: lfdx 1,
 ; CHECK: mtvsrd 1, 3
 }

diff --git a/test/CodeGen/PowerPC/branch_coalesce.ll b/test/CodeGen/PowerPC/branch_coalesce.ll
index a57dec1..c4666d3 100644 (file)
--- a/test/CodeGen/PowerPC/branch_coalesce.ll
+++ b/test/CodeGen/PowerPC/branch_coalesce.ll
@@ -15,8 +15,8 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 ; CHECK-NOT: beq
 ; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]]
 ; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]]
-; CHECK-DAG: lxsdx 1, 0, [[LD1BASE]]
-; CHECK-DAG: lxsdx 3, 0, [[LD2BASE]]
+; CHECK-DAG: lfdx 1, 0, [[LD1BASE]]
+; CHECK-DAG: lfdx 3, 0, [[LD2BASE]]
 ; CHECK: .LBB[[LAB1]]
 ; CHECK: xsadddp 0, 1, 2
 ; CHECK: xsadddp 1, 0, 3
@@ -33,7 +33,7 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_3: # %entry
 ; CHECK-NOCOALESCE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; CHECK-NOCOALESCE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; CHECK-NOCOALESCE-NEXT:    lxsdx 3, 0, 3
+; CHECK-NOCOALESCE-NEXT:    lfdx 3, 0, 3
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_4: # %entry
 ; CHECK-NOCOALESCE-NEXT:    xsadddp 0, 1, 2
 ; CHECK-NOCOALESCE-NEXT:    xsadddp 1, 0, 3
@@ -41,7 +41,7 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_5: # %entry
 ; CHECK-NOCOALESCE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NOCOALESCE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-NOCOALESCE-NEXT:    lxsdx 1, 0, 3
+; CHECK-NOCOALESCE-NEXT:    lfdx 1, 0, 3
 ; CHECK-NOCOALESCE-NEXT:    beq 0, .LBB0_2
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_6: # %entry
 ; CHECK-NOCOALESCE-NEXT:    xxlxor 2, 2, 2

diff --git a/test/CodeGen/PowerPC/build-vector-tests.ll b/test/CodeGen/PowerPC/build-vector-tests.ll
index 16b562b..d54e24d 100644 (file)
--- a/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -1667,20 +1667,20 @@ entry:
 ; P9LE: xvcvdpsp
 ; P9LE: vmrgew
 ; P9LE: xvcvspsxws v2
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
 ; P8BE: xvcvdpsp
 ; P8BE: vmrgew
 ; P8BE: xvcvspsxws v2
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp
@@ -1741,9 +1741,9 @@ entry:
 ; P9LE: vmrgew
 ; P9LE: xvcvspsxws v2
 ; P8BE: lfdux
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
@@ -1751,9 +1751,9 @@ entry:
 ; P8BE: vmrgew
 ; P8BE: xvcvspsxws v2
 ; P8LE: lfdux
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp
@@ -1814,9 +1814,9 @@ entry:
 ; P9LE: vmrgew
 ; P9LE: xvcvspsxws v2
 ; P8BE: lfdux
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
@@ -1824,9 +1824,9 @@ entry:
 ; P8BE: vmrgew
 ; P8BE: xvcvspsxws v2
 ; P8LE: lfdux
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp
@@ -2827,20 +2827,20 @@ entry:
 ; P9LE: xvcvdpsp
 ; P9LE: vmrgew
 ; P9LE: xvcvspuxws v2
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
 ; P8BE: xvcvdpsp
 ; P8BE: vmrgew
 ; P8BE: xvcvspuxws v2
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp
@@ -2901,9 +2901,9 @@ entry:
 ; P9LE: vmrgew
 ; P9LE: xvcvspuxws v2
 ; P8BE: lfdux
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
@@ -2911,9 +2911,9 @@ entry:
 ; P8BE: vmrgew
 ; P8BE: xvcvspuxws v2
 ; P8LE: lfdux
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp
@@ -2974,9 +2974,9 @@ entry:
 ; P9LE: vmrgew
 ; P9LE: xvcvspuxws v2
 ; P8BE: lfdux
-; P8BE: lxsdx
-; P8BE: lxsdx
-; P8BE: lxsdx
+; P8BE: lfd
+; P8BE: lfd
+; P8BE: lfd
 ; P8BE: xxmrghd
 ; P8BE: xxmrghd
 ; P8BE: xvcvdpsp
@@ -2984,9 +2984,9 @@ entry:
 ; P8BE: vmrgew
 ; P8BE: xvcvspuxws v2
 ; P8LE: lfdux
-; P8LE: lxsdx
-; P8LE: lxsdx
-; P8LE: lxsdx
+; P8LE: lfd
+; P8LE: lfd
+; P8LE: lfd
 ; P8LE: xxmrghd
 ; P8LE: xxmrghd
 ; P8LE: xvcvdpsp

diff --git a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
index 8a873da..8a95de3 100644 (file)
--- a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
+++ b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
@@ -17,7 +17,7 @@ entry:
   %this.addr = alloca %SomeStruct*, align 8
   %V.addr = alloca double, align 8
   store %SomeStruct* %this, %SomeStruct** %this.addr, align 8
-; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
+; ELF64VSX: stfdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
   store double %V, double* %V.addr, align 8
   %this1 = load %SomeStruct*, %SomeStruct** %this.addr
   %Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0

diff --git a/test/CodeGen/PowerPC/float-to-int.ll b/test/CodeGen/PowerPC/float-to-int.ll
index 80e6b75..6249c94 100644 (file)
--- a/test/CodeGen/PowerPC/float-to-int.ll
+++ b/test/CodeGen/PowerPC/float-to-int.ll
@@ -21,7 +21,7 @@ define i64 @foo(float %a) nounwind {
 
 ; CHECK-VSX: @foo
 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
-; CHECK-VSX: stxsdx [[REG]],
+; CHECK-VSX: stfdx [[REG]],
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
@@ -44,7 +44,7 @@ define i64 @foo2(double %a) nounwind {
 
 ; CHECK-VSX: @foo2
 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
-; CHECK-VSX: stxsdx [[REG]],
+; CHECK-VSX: stfdx [[REG]],
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
@@ -67,7 +67,7 @@ define i64 @foo3(float %a) nounwind {
 
 ; CHECK-VSX: @foo3
 ; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
-; CHECK-VSX: stxsdx [[REG]],
+; CHECK-VSX: stfdx [[REG]],
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 
@@ -90,7 +90,7 @@ define i64 @foo4(double %a) nounwind {
 
 ; CHECK-VSX: @foo4
 ; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
-; CHECK-VSX: stxsdx [[REG]],
+; CHECK-VSX: stfdx [[REG]],
 ; CHECK-VSX: ld 3,
 ; CHECK-VSX: blr
 

diff --git a/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
index cd4eac4..b630159 100644 (file)
--- a/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
+++ b/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -7,8 +7,8 @@
 define i128 @test_abs(ppc_fp128 %x) nounwind  {
 entry:
 ; PPC64-LABEL: test_abs:
-; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
-; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
+; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
+; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
@@ -45,8 +45,8 @@ entry:
 define i128 @test_neg(ppc_fp128 %x) nounwind  {
 entry:
 ; PPC64-LABEL: test_neg:
-; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
-; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
+; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
+; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
 ; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
@@ -87,7 +87,7 @@ entry:
 define i128 @test_copysign(ppc_fp128 %x) nounwind  {
 entry:
 ; PPC64-LABEL: test_copysign:
-; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]]
+; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
 ; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48

diff --git a/test/CodeGen/PowerPC/i64-to-float.ll b/test/CodeGen/PowerPC/i64-to-float.ll
index e139579..b15f1f8 100644 (file)
--- a/test/CodeGen/PowerPC/i64-to-float.ll
+++ b/test/CodeGen/PowerPC/i64-to-float.ll
@@ -20,7 +20,7 @@ entry:
 
 ; CHECK-VSX: @foo
 ; CHECK-VSX: std 3,
-; CHECK-VSX: lxsdx [[REG:[0-9]+]],
+; CHECK-VSX: lfdx [[REG:[0-9]+]],
 ; CHECK-VSX: fcfids 1, [[REG]]
 ; CHECK-VSX: blr
 
@@ -44,7 +44,7 @@ entry:
 
 ; CHECK-VSX: @goo
 ; CHECK-VSX: std 3,
-; CHECK-VSX: lxsdx [[REG:[0-9]+]],
+; CHECK-VSX: lfdx [[REG:[0-9]+]],
 ; CHECK-VSX: xscvsxddp 1, [[REG]]
 ; CHECK-VSX: blr
 
@@ -68,7 +68,7 @@ entry:
 
 ; CHECK-VSX: @foou
 ; CHECK-VSX: std 3,
-; CHECK-VSX: lxsdx [[REG:[0-9]+]],
+; CHECK-VSX: lfdx [[REG:[0-9]+]],
 ; CHECK-VSX: fcfidus 1, [[REG]]
 ; CHECK-VSX: blr
 
@@ -92,7 +92,7 @@ entry:
 
 ; CHECK-VSX: @goou
 ; CHECK-VSX: std 3,
-; CHECK-VSX: lxsdx [[REG:[0-9]+]],
+; CHECK-VSX: lfdx [[REG:[0-9]+]],
 ; CHECK-VSX: xscvuxddp 1, [[REG]]
 ; CHECK-VSX: blr
 

diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll
index c07dbd9..f6b54c3 100644 (file)
--- a/test/CodeGen/PowerPC/mcm-12.ll
+++ b/test/CodeGen/PowerPC/mcm-12.ll
@@ -27,7 +27,7 @@ entry:
 ; CHECK-VSX-LABEL: test_double_const:
 ; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK-VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
-; CHECK-VSX: lxsdx {{[0-9]+}}, 0, [[REG1]]
+; CHECK-VSX: lfdx {{[0-9]+}}, 0, [[REG1]]
 
 ; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
 ; CHECK-P9: .quad 4562098671269285104

diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll
index 180977d..c335fff 100644 (file)
--- a/test/CodeGen/PowerPC/mcm-4.ll
+++ b/test/CodeGen/PowerPC/mcm-4.ll
@@ -34,7 +34,7 @@ entry:
 ; MEDIUM-VSX-LABEL: test_double_const:
 ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
-; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
+; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
@@ -48,7 +48,7 @@ entry:
 ; LARGE-VSX-LABEL: test_double_const:
 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
-; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
+; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
 
 ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM-P9: .quad 4562098671269285104

diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
index 1bf208d..ec11b54 100644 (file)
--- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -46,8 +46,8 @@ entry:
 ; CHECK-VSX-DAG: std 6, -8(1)
 ; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16
 ; CHECK-VSX-DAG: addi 3, 1, -8
-; CHECK-VSX: lxsdx 1, 0, [[REG1]]
-; CHECK-VSX: lxsdx 2, 0, 3
+; CHECK-VSX: lfdx 1, 0, [[REG1]]
+; CHECK-VSX: lfdx 2, 0, 3
 
 ; FIXME-VSX: addi 4, 1, 48
 ; FIXME-VSX: lxsdx 1, 4, 3

diff --git a/test/CodeGen/PowerPC/pr30715.ll b/test/CodeGen/PowerPC/pr30715.ll
index 5d6ba2c..96fb786 100644 (file)
--- a/test/CodeGen/PowerPC/pr30715.ll
+++ b/test/CodeGen/PowerPC/pr30715.ll
@@ -67,7 +67,7 @@ for.body:                                         ; preds = %for.body.preheader,
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
   br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
-; CHECK: stxsdx
+; CHECK: stfdx
 ; CHECK: lxvd2x
 }
 

diff --git a/test/CodeGen/PowerPC/select_const.ll b/test/CodeGen/PowerPC/select_const.ll
index 178d918..08dfce4 100644 (file)
--- a/test/CodeGen/PowerPC/select_const.ll
+++ b/test/CodeGen/PowerPC/select_const.ll
@@ -652,7 +652,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-NEXT:    addi 4, 4, .LCPI34_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI34_1@toc@l
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fadd_constant:
@@ -667,7 +667,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB34_2
 ; NO_ISEL-NEXT:  .LBB34_2:
-; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fadd double %sel, 5.1
@@ -683,7 +683,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-NEXT:    addi 4, 4, .LCPI35_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI35_1@toc@l
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fsub_constant:
@@ -698,7 +698,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB35_2
 ; NO_ISEL-NEXT:  .LBB35_2:
-; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double %sel, 5.1
@@ -714,7 +714,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-NEXT:    addi 4, 4, .LCPI36_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI36_1@toc@l
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fmul_constant:
@@ -729,7 +729,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB36_2
 ; NO_ISEL-NEXT:  .LBB36_2:
-; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fmul double %sel, 5.1
@@ -745,7 +745,7 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-NEXT:    addi 4, 4, .LCPI37_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI37_1@toc@l
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
@@ -760,7 +760,7 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB37_2
 ; NO_ISEL-NEXT:  .LBB37_2:
-; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    lfdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double %sel, 5.1
@@ -775,7 +775,7 @@ define double @sel_constants_frem_constant(i1 %cond) {
 ; ALL-NEXT:  # %bb.1:
 ; ALL-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
 ; ALL-NEXT:    addi 3, 3, .LCPI38_0@toc@l
-; ALL-NEXT:    lxsdx 1, 0, 3
+; ALL-NEXT:    lfdx 1, 0, 3
 ; ALL-NEXT:    blr
 ; ALL-NEXT:  .LBB38_2:
 ; ALL-NEXT:    addis 3, 2, .LCPI38_1@toc@ha

diff --git a/test/CodeGen/PowerPC/store_fptoi.ll b/test/CodeGen/PowerPC/store_fptoi.ll
index 2c6d70a..bac874a 100644 (file)
--- a/test/CodeGen/PowerPC/store_fptoi.ll
+++ b/test/CodeGen/PowerPC/store_fptoi.ll
@@ -22,7 +22,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sdw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
 ; CHECK-PWR8-NEXT: blr
@@ -43,7 +43,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
 ; CHECK-PWR8-NEXT: blr
@@ -64,7 +64,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2shw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
@@ -86,7 +86,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sb
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
@@ -198,7 +198,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sdw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
 ; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
@@ -224,7 +224,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
@@ -250,7 +250,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2shw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
@@ -276,7 +276,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2sb_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
@@ -406,7 +406,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2udw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
 ; CHECK-PWR8-NEXT: blr
@@ -427,7 +427,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
 ; CHECK-PWR8-NEXT: blr
@@ -448,7 +448,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uhw
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
@@ -470,7 +470,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2ub
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
@@ -582,7 +582,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2udw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
 ; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
@@ -608,7 +608,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
 ; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
@@ -634,7 +634,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2uhw_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
@@ -660,7 +660,7 @@ entry:
 ; CHECK-NEXT: blr
 
 ; CHECK-PWR8-LABEL: dpConv2ub_x
-; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
+; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5

diff --git a/test/CodeGen/PowerPC/swaps-le-6.ll b/test/CodeGen/PowerPC/swaps-le-6.ll
index d573441..82c240e 100644 (file)
--- a/test/CodeGen/PowerPC/swaps-le-6.ll
+++ b/test/CodeGen/PowerPC/swaps-le-6.ll
@@ -27,7 +27,7 @@ entry:
 
 ; CHECK-LABEL: @bar0
 ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
-; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
+; CHECK-DAG: lfdx [[REG2:[0-9]+]]
 ; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
 ; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
 ; CHECK: stxvd2x [[REG5]]
@@ -50,7 +50,7 @@ entry:
 
 ; CHECK-LABEL: @bar1
 ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
-; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
+; CHECK-DAG: lfdx [[REG2:[0-9]+]]
 ; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
 ; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
 ; CHECK: stxvd2x [[REG5]]

diff --git a/test/CodeGen/PowerPC/unaligned.ll b/test/CodeGen/PowerPC/unaligned.ll
index c9f65f2..bd51834 100644 (file)
--- a/test/CodeGen/PowerPC/unaligned.ll
+++ b/test/CodeGen/PowerPC/unaligned.ll
@@ -74,8 +74,8 @@ entry:
 ; CHECK: stfd
 
 ; CHECK-VSX: @foo5
-; CHECK-VSX: lxsdx
-; CHECK-VSX: stxsdx
+; CHECK-VSX: lfdx
+; CHECK-VSX: stfdx
 }
 
 define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {

diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
index 0a4db39..df4cf35 100644 (file)
--- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
+++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
@@ -16,7 +16,7 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
 
 ; CHECK-LABEL: testi0
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: lxsdx 1, 0, 4
+; CHECK: lfdx 1, 0, 4
 ; CHECK-DAG: xxspltd 1, 1, 0
 ; CHECK-DAG: xxswapd 0, 0
 ; CHECK: xxpermdi 34, 0, 1, 1
@@ -36,7 +36,7 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
 
 ; CHECK-LABEL: testi1
 ; CHECK: lxvd2x 0, 0, 3
-; CHECK: lxsdx 1, 0, 4
+; CHECK: lfdx 1, 0, 4
 ; CHECK-DAG: xxspltd 1, 1, 0
 ; CHECK-DAG: xxswapd 0, 0
 ; CHECK: xxmrgld 34, 1, 0

diff --git a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
index d8ea0dc..ec6646d 100644 (file)
--- a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
+++ b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
@@ -123,7 +123,7 @@ entry:
   store volatile float %conv, float* %ff, align 4
   ret void
 ; CHECK-LABEL: @dblToFloat
-; CHECK: lxsdx [[REGLD5:[0-9]+]],
+; CHECK: lfdx [[REGLD5:[0-9]+]],
 ; CHECK: stfsx [[REGLD5]],
 ; CHECK-P9-LABEL: @dblToFloat
 ; CHECK-P9: lfd [[REGLD5:[0-9]+]],
@@ -140,7 +140,7 @@ entry:
   ret void
 ; CHECK-LABEL: @floatToDbl
 ; CHECK: lfsx [[REGLD5:[0-9]+]],
-; CHECK: stxsdx [[REGLD5]],
+; CHECK: stfdx [[REGLD5]],
 ; CHECK-P9-LABEL: @floatToDbl
 ; CHECK-P9: lfs [[REGLD5:[0-9]+]],
 ; CHECK-P9: stfd [[REGLD5]],