abs, x working.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 92295e7..fb6b3a0 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -45,6 +45,7 @@ entity effective_adder is
     generic (   dsize : integer := 8
             );
     port (  
+            clk         : in std_logic;
             ah_oe_n         : in std_logic;
             al_oe_n         : in std_logic;
             base            : in std_logic_vector (dsize - 1 downto 0);
@@ -56,15 +57,40 @@ entity effective_adder is
 end effective_adder;
 
 architecture rtl of effective_adder is
-signal d_out : std_logic_vector (dsize - 1 downto 0);
+    component dff
+        generic (
+                dsize : integer := 8
+                );
+        port (  
+                clk     : in std_logic;
+                we_n    : in std_logic;
+                oe_n    : in std_logic;
+                d       : in std_logic_vector (dsize - 1 downto 0);
+                q       : out std_logic_vector (dsize - 1 downto 0)
+            );
+    end component;
+
+signal al_out : std_logic_vector (dsize - 1 downto 0);
+signal ah_out : std_logic_vector (dsize - 1 downto 0);
+signal old_al : std_logic_vector (dsize - 1 downto 0);
 signal adc_work : std_logic_vector (dsize downto 0);
+
 begin
     adc_work <= ('0' & base) + ('0' & index);
     carry <= adc_work(dsize);
-    d_out <= adc_work(dsize - 1 downto 0);
-    ah_bus <= d_out when ah_oe_n = '0' else
+    al_out <= adc_work(dsize - 1 downto 0);
+    ---always remory adl.
+    al_buf : dff generic map (dsize)
+        port map (clk, '0', '0', al_out, old_al);
+
+    --both output means, page boundary crossed.
+    --output old effective addr low.
+    al_bus <= old_al when al_oe_n = '0' and ah_oe_n = '0' else
+            al_out when al_oe_n = '0' else
             (others => 'Z');
-    al_bus <= d_out when al_oe_n = '0' else
+
+    --ah output means, page boundary crossed.
+    ah_bus <= base + '1' when ah_oe_n = '0' else
             (others => 'Z');
 
 end rtl;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index ba59f3c..c3cb127 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -310,6 +310,8 @@ begin
                 dl_dl_oe_n <= '1';
                 x_calc_n <= '1';
                 ea_al_oe_n <= '1';
+                dl_dh_oe_n <= '1';
+                ea_ah_oe_n <= '1';
 
                 cur_cycle <= decode;
 
@@ -718,7 +720,7 @@ begin
                         dbuf_int_oe_n <= '1';
                         dl_ah_we_n <= '1';
 
-                        -----calucurate and output effective addr 
+                        -----calucurate and output effective addr low
                         dl_dl_oe_n <= '0';
                         x_calc_n <= '0';
                         ea_al_oe_n <= '0';
@@ -773,10 +775,19 @@ begin
                     ---conditional branch instruction..
                 else
                     if cur_mode = ad_absx then
-                        if ea_carry = '1' then
+                        if ea_carry = '0' then
                             --case page boundary crossed.
+                            d_print("absx 5 (page boudary crossed.)");
+                            dl_dl_oe_n <= '1';
+                            dl_ah_oe_n <= '1';
+
                             --increment eah.
-                            d_print("absx 5");
+                            -----effective addr low is remorized in the calc.
+                            dl_dh_oe_n <= '0';
+                            x_calc_n <= '0';
+                            ea_al_oe_n <= '0';
+                            ea_ah_oe_n <= '0';
+                            cur_cycle <= fetch;
                         else
                             --case page boundary not crossed. do the fetch op.
                             d_print("absx 5 (fetch)");
@@ -785,6 +796,7 @@ begin
                             ea_al_oe_n <= '1';
                             dl_ah_oe_n <= '1';
                             acc_d_we_n  <= '1';
+                            dl_al_we_n <= '1';
 
                             pcl_a_oe_n <= '0';
                             pch_a_oe_n <= '0';
@@ -792,6 +804,17 @@ begin
                         end if;
                     end if;
                     if instruction (1 downto 0) = "00" then
+                    elsif instruction (1 downto 0) = "01" then
+                        if instruction (7 downto 5) = "100" then
+                            d_print("sta 5");
+                            --output acc memory..
+                            r_nw <= '0';
+                            acc_d_oe_n  <= '0';
+                        elsif instruction (7 downto 5) = "101" then
+                            d_print("lda 5");
+                            --if page boundary is crossed, redo in the next cycle.
+                            acc_d_we_n  <= '0';
+                        end if;
                     end if; --instruction (1 downto 0) = "00" 
                 end if; --if instruction = conv_std_logic_vector(16#00#, dsize) 
  

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index a1d833a..146d6ff 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -204,6 +204,7 @@ architecture rtl of mos6502 is
     generic (   dsize : integer := 8
             );
     port (  
+            clk         : in std_logic;
             ah_oe_n         : in std_logic;
             al_oe_n         : in std_logic;
             base            : in std_logic_vector (dsize - 1 downto 0);
@@ -387,8 +388,9 @@ begin
     y_buf_addr : tsb generic map (dsize)
             port map (y_calc_n, y_out, addr_index);
 
+    ---effective addres calcurator.
     addr_calc: effective_adder generic map (dsize)
-            port map (ea_ah_oe_n, ea_al_oe_n,
+            port map (trigger_clk, ea_ah_oe_n, ea_al_oe_n,
                     internal_dbus, addr_index, 
                     internal_abus_h, internal_abus_l, ea_carry);