drm/amd/display/dm: add picasso support

Add support for picasso to the display manager.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 82c2e82..25e7e1c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2177,6 +2177,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
        case CHIP_VEGA20:
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case CHIP_RAVEN:
+       case CHIP_PICASSO:
 #endif
                return amdgpu_dc != 0;
 #endif

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 23ddf54..1ff2e8f 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1213,7 +1213,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
        if (adev->asic_type == CHIP_VEGA10 ||
            adev->asic_type == CHIP_VEGA12 ||
            adev->asic_type == CHIP_VEGA20 ||
-           adev->asic_type == CHIP_RAVEN)
+           adev->asic_type == CHIP_RAVEN  ||
+           adev->asic_type == CHIP_PICASSO)
                client_id = SOC15_IH_CLIENTID_DCE;
 
        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1632,6 +1633,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case CHIP_RAVEN:
+       case CHIP_PICASSO:
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -1858,6 +1860,7 @@ static int dm_early_init(void *handle)
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case CHIP_RAVEN:
+       case CHIP_PICASSO:
                adev->mode_info.num_crtc = 4;
                adev->mode_info.num_hpd = 4;
                adev->mode_info.num_dig = 4;
@@ -2106,7 +2109,8 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
        if (adev->asic_type == CHIP_VEGA10 ||
            adev->asic_type == CHIP_VEGA12 ||
            adev->asic_type == CHIP_VEGA20 ||
-           adev->asic_type == CHIP_RAVEN) {
+           adev->asic_type == CHIP_RAVEN  ||
+           adev->asic_type == CHIP_PICASSO) {
                /* Fill GFX9 params */
                plane_state->tiling_info.gfx9.num_pipes =
                        adev->gfx.config.gb_addr_config_fields.num_pipes;