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drm/i915/glk: Program new MIPI DSI PHY registers for GLK
authorDeepak M <m.deepak@intel.com>
Fri, 17 Feb 2017 12:43:30 +0000 (18:13 +0530)
committerJani Nikula <jani.nikula@intel.com>
Tue, 28 Feb 2017 09:31:17 +0000 (11:31 +0200)
Program the clk lane and tlpx time count registers
to configure DSI PHY.

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-3-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dsi.c

index bdce900..31e38ce 100644 (file)
@@ -8625,6 +8625,14 @@ enum {
 #define  LP_BYTECLK_SHIFT                              0
 #define  LP_BYTECLK_MASK                               (0xffff << 0)
 
+#define _MIPIA_TLPX_TIME_COUNT         (dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT         (dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port)      _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+
+#define _MIPIA_CLK_LANE_TIMING         (dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING         (dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port)      _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+
 /* bits 31:0 */
 #define _MIPIA_LP_GEN_DATA             (dev_priv->mipi_mmio_base + 0xb064)
 #define _MIPIC_LP_GEN_DATA             (dev_priv->mipi_mmio_base + 0xb864)
index d7ffb9a..f00b4e2 100644 (file)
@@ -1309,6 +1309,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
                 */
                I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 
+               if (IS_GEMINILAKE(dev_priv)) {
+                       I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
+                                       intel_dsi->lp_byte_clk);
+                       /* Shadow of DPHY reg */
+                       I915_WRITE(MIPI_CLK_LANE_TIMING(port),
+                                       intel_dsi->dphy_reg);
+               }
+
                /* the bw essential for transmitting 16 long packets containing
                 * 252 bytes meant for dcs write memory command is programmed in
                 * this register in terms of byte clocks. based on dsi transfer