ARM: dts: msm: Correct csiphy clocks and clock rates on msmcobalt

Use proper mmss clock for csiphy and set the phytimer clock rate at
200MHz.Update csiphy node with regulators needed by csiphy clocks.

CRs-Fixed: 1068060
Change-Id: Iaf8240c2a6ef0b7739f80b6d0bb30946f61a9ed0
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>

diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
index 99d80a3..fcc4d6d 100644 (file)
--- a/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
@@ -19,7 +19,10 @@
                reg-names = "csiphy";
                interrupts = <0 78 0>;
                interrupt-names = "csiphy";
-               clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+               gdscr-supply = <&gdsc_camss_top>;
+               bimc_smmu-supply = <&gdsc_bimc_smmu>;
+               qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+               clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
                        <&clock_mmss clk_mmss_mnoc_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -33,13 +36,13 @@
                        <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
                        <&clock_mmss clk_csiphy_clk_src>,
                        <&clock_mmss clk_mmss_camss_csiphy0_clk>;
-               clock-names = "mnoc_maxi", "mnoc_ahb",
+               clock-names = "mmssnoc_axi", "mnoc_ahb",
                        "bmic_smmu_ahb", "bmic_smmu_axi",
                        "camss_ahb_clk", "camss_top_ahb_clk",
                        "csi_src_clk", "csi_clk", "cphy_csid_clk",
                        "csiphy_timer_src_clk", "csiphy_timer_clk",
                        "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
-               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
                        0 256000000 0>;
                status = "ok";
        };
@@ -51,7 +54,10 @@
                reg-names = "csiphy";
                interrupts = <0 79 0>;
                interrupt-names = "csiphy";
-               clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+               gdscr-supply = <&gdsc_camss_top>;
+               bimc_smmu-supply = <&gdsc_bimc_smmu>;
+               qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+               clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
                        <&clock_mmss clk_mmss_mnoc_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -65,13 +71,13 @@
                        <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
                        <&clock_mmss clk_csiphy_clk_src>,
                        <&clock_mmss clk_mmss_camss_csiphy1_clk>;
-               clock-names = "mnoc_maxi", "mnoc_ahb",
+               clock-names = "mmssnoc_axi", "mnoc_ahb",
                        "bmic_smmu_ahb", "bmic_smmu_axi",
                        "camss_ahb_clk", "camss_top_ahb_clk",
                        "csi_src_clk", "csi_clk", "cphy_csid_clk",
                        "csiphy_timer_src_clk", "csiphy_timer_clk",
                        "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
-               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
                        0 256000000 0>;
                status = "ok";
        };
@@ -83,7 +89,10 @@
                reg-names = "csiphy";
                interrupts = <0 80 0>;
                interrupt-names = "csiphy";
-               clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+               gdscr-supply = <&gdsc_camss_top>;
+               bimc_smmu-supply = <&gdsc_bimc_smmu>;
+               qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+               clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
                        <&clock_mmss clk_mmss_mnoc_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
                        <&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -97,13 +106,13 @@
                        <&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
                        <&clock_mmss clk_csiphy_clk_src>,
                        <&clock_mmss clk_mmss_camss_csiphy2_clk>;
-               clock-names = "mnoc_maxi", "mnoc_ahb",
+               clock-names = "mmssnoc_axi", "mnoc_ahb",
                        "bmic_smmu_ahb", "bmic_smmu_axi",
                        "camss_ahb_clk", "camss_top_ahb_clk",
                        "csi_src_clk", "csi_clk", "cphy_csid_clk",
                        "csiphy_timer_src_clk", "csiphy_timer_clk",
                        "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
-               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
+               qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
                        0 256000000 0>;
                status = "ok";
        };