ARM: dts: Configure interconnect target module for am3 aes

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 0d7323b..7db9f72 100644 (file)
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -468,14 +468,35 @@
                        };
                };
 
-               aes: aes@53500000 {
-                       compatible = "ti,omap4-aes";
+               aes_target: target-module@53500000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
                        ti,hwmods = "aes";
-                       reg = <0x53500000 0xa0>;
-                       interrupts = <103>;
-                       dmas = <&edma 6 0>,
-                              <&edma 5 0>;
-                       dma-names = "tx", "rx";
+                       reg = <0x53500080 0x4>,
+                             <0x53500084 0x4>,
+                             <0x53500088 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): per_pwrdm, l3_clkdm */
+                       clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x53500000 0x1000>;
+
+                       aes: aes@0 {
+                               compatible = "ti,omap4-aes";
+                               reg = <0 0xa0>;
+                               interrupts = <103>;
+                               dmas = <&edma 6 0>,
+                                      <&edma 5 0>;
+                               dma-names = "tx", "rx";
+                       };
                };
        };
 };