; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
%valadd = add i128 %a, %b
; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
}
define i128 @test_imm(i128 %a) {
-; CHECK: test_imm:
+; CHECK-LABEL: test_imm:
%val = add i128 %a, 12
; CHECK: adds x0, x0, #12
}
define i128 @test_shifted(i128 %a, i128 %b) {
-; CHECK: test_shifted:
+; CHECK-LABEL: test_shifted:
%rhs = shl i128 %b, 45
}
define i128 @test_extended(i128 %a, i16 %b) {
-; CHECK: test_extended:
+; CHECK-LABEL: test_extended:
%ext = sext i16 %b to i128
%rhs = shl i128 %ext, 3
@var64 = global i64 0
define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsl_arith:
+; CHECK-LABEL: test_lsl_arith:
%rhs1 = load volatile i32* @var32
%shift1 = shl i32 %rhs1, 18
}
define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsr_arith:
+; CHECK-LABEL: test_lsr_arith:
%shift1 = lshr i32 %rhs32, 18
%val1 = add i32 %lhs32, %shift1
}
define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_asr_arith:
+; CHECK-LABEL: test_asr_arith:
%shift1 = ashr i32 %rhs32, 18
%val1 = add i32 %lhs32, %shift1
}
define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmp:
+; CHECK-LABEL: test_cmp:
%shift1 = shl i32 %rhs32, 13
%tst1 = icmp uge i32 %lhs32, %shift1
}
define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmn:
+; CHECK-LABEL: test_cmn:
%shift1 = shl i32 %rhs32, 13
%val1 = sub i32 0, %shift1
}
define void @testing() {
-; CHECK: testing:
+; CHECK-LABEL: testing:
%val = load i32* @var_i32
; CHECK: cmp {{w[0-9]+}}, #4095
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
ret void
-}
\ No newline at end of file
+}
declare void @use_addr(i8*)
define void @test_simple_alloca(i64 %n) {
-; CHECK: test_simple_alloca:
+; CHECK-LABEL: test_simple_alloca:
%buf = alloca i8, i64 %n
; Make sure we align the stack change to 16 bytes:
declare void @use_addr_loc(i8*, i64*)
define i64 @test_alloca_with_local(i64 %n) {
-; CHECK: test_alloca_with_local:
+; CHECK-LABEL: test_alloca_with_local:
; CHECK: sub sp, sp, #32
; CHECK: stp x29, x30, [sp, #16]
}
define void @test_variadic_alloca(i64 %n, ...) {
-; CHECK: test_variadic_alloca:
+; CHECK-LABEL: test_variadic_alloca:
; CHECK: sub sp, sp, #208
; CHECK: stp x29, x30, [sp, #192]
}
define void @test_alloca_large_frame(i64 %n) {
-; CHECK: test_alloca_large_frame:
+; CHECK-LABEL: test_alloca_large_frame:
; CHECK: sub sp, sp, #496
; CHECK: stp x29, x30, [sp, #480]
!1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_taken:
+; CHECK-LABEL: test_Bcc_fallthrough_taken:
%tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !0
}
define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_nottaken:
+; CHECK-LABEL: test_Bcc_fallthrough_nottaken:
%tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !1
}
define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_taken:
+; CHECK-LABEL: test_CBZ_fallthrough_taken:
%tst = icmp eq i32 %in, 0
br i1 %tst, label %true, label %false, !prof !0
}
define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBZ_fallthrough_nottaken:
%tst = icmp eq i64 %in, 0
br i1 %tst, label %true, label %false, !prof !1
}
define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_taken:
+; CHECK-LABEL: test_CBNZ_fallthrough_taken:
%tst = icmp ne i32 %in, 0
br i1 %tst, label %true, label %false, !prof !0
}
define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBNZ_fallthrough_nottaken:
%tst = icmp ne i64 %in, 0
br i1 %tst, label %true, label %false, !prof !1
}
define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_taken:
+; CHECK-LABEL: test_TBZ_fallthrough_taken:
%bit = and i32 %in, 32768
%tst = icmp eq i32 %bit, 0
br i1 %tst, label %true, label %false, !prof !0
}
define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBZ_fallthrough_nottaken:
%bit = and i64 %in, 32768
%tst = icmp eq i64 %bit, 0
br i1 %tst, label %true, label %false, !prof !1
define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_taken:
+; CHECK-LABEL: test_TBNZ_fallthrough_taken:
%bit = and i32 %in, 32768
%tst = icmp ne i32 %bit, 0
br i1 %tst, label %true, label %false, !prof !0
}
define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBNZ_fallthrough_nottaken:
%bit = and i64 %in, 32768
%tst = icmp ne i64 %bit, 0
br i1 %tst, label %true, label %false, !prof !1
@var64 = global i64 0
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_add_i8:
+; CHECK-LABEL: test_atomic_load_add_i8:
%old = atomicrmw add i8* @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_add_i16:
+; CHECK-LABEL: test_atomic_load_add_i16:
%old = atomicrmw add i16* @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_add_i32:
+; CHECK-LABEL: test_atomic_load_add_i32:
%old = atomicrmw add i32* @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_add_i64:
+; CHECK-LABEL: test_atomic_load_add_i64:
%old = atomicrmw add i64* @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i8:
+; CHECK-LABEL: test_atomic_load_sub_i8:
%old = atomicrmw sub i8* @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i16:
+; CHECK-LABEL: test_atomic_load_sub_i16:
%old = atomicrmw sub i16* @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i32:
+; CHECK-LABEL: test_atomic_load_sub_i32:
%old = atomicrmw sub i32* @var32, i32 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i64:
+; CHECK-LABEL: test_atomic_load_sub_i64:
%old = atomicrmw sub i64* @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_and_i8:
+; CHECK-LABEL: test_atomic_load_and_i8:
%old = atomicrmw and i8* @var8, i8 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_and_i16:
+; CHECK-LABEL: test_atomic_load_and_i16:
%old = atomicrmw and i16* @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_and_i32:
+; CHECK-LABEL: test_atomic_load_and_i32:
%old = atomicrmw and i32* @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_and_i64:
+; CHECK-LABEL: test_atomic_load_and_i64:
%old = atomicrmw and i64* @var64, i64 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_or_i8:
+; CHECK-LABEL: test_atomic_load_or_i8:
%old = atomicrmw or i8* @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_or_i16:
+; CHECK-LABEL: test_atomic_load_or_i16:
%old = atomicrmw or i16* @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_or_i32:
+; CHECK-LABEL: test_atomic_load_or_i32:
%old = atomicrmw or i32* @var32, i32 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_or_i64:
+; CHECK-LABEL: test_atomic_load_or_i64:
%old = atomicrmw or i64* @var64, i64 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i8:
+; CHECK-LABEL: test_atomic_load_xor_i8:
%old = atomicrmw xor i8* @var8, i8 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i16:
+; CHECK-LABEL: test_atomic_load_xor_i16:
%old = atomicrmw xor i16* @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i32:
+; CHECK-LABEL: test_atomic_load_xor_i32:
%old = atomicrmw xor i32* @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i64:
+; CHECK-LABEL: test_atomic_load_xor_i64:
%old = atomicrmw xor i64* @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i8:
+; CHECK-LABEL: test_atomic_load_xchg_i8:
%old = atomicrmw xchg i8* @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i16:
+; CHECK-LABEL: test_atomic_load_xchg_i16:
%old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i32:
+; CHECK-LABEL: test_atomic_load_xchg_i32:
%old = atomicrmw xchg i32* @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i64:
+; CHECK-LABEL: test_atomic_load_xchg_i64:
%old = atomicrmw xchg i64* @var64, i64 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_min_i8:
+; CHECK-LABEL: test_atomic_load_min_i8:
%old = atomicrmw min i8* @var8, i8 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_min_i16:
+; CHECK-LABEL: test_atomic_load_min_i16:
%old = atomicrmw min i16* @var16, i16 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_min_i32:
+; CHECK-LABEL: test_atomic_load_min_i32:
%old = atomicrmw min i32* @var32, i32 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_min_i64:
+; CHECK-LABEL: test_atomic_load_min_i64:
%old = atomicrmw min i64* @var64, i64 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_max_i8:
+; CHECK-LABEL: test_atomic_load_max_i8:
%old = atomicrmw max i8* @var8, i8 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_max_i16:
+; CHECK-LABEL: test_atomic_load_max_i16:
%old = atomicrmw max i16* @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_max_i32:
+; CHECK-LABEL: test_atomic_load_max_i32:
%old = atomicrmw max i32* @var32, i32 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_max_i64:
+; CHECK-LABEL: test_atomic_load_max_i64:
%old = atomicrmw max i64* @var64, i64 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i8:
+; CHECK-LABEL: test_atomic_load_umin_i8:
%old = atomicrmw umin i8* @var8, i8 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i16:
+; CHECK-LABEL: test_atomic_load_umin_i16:
%old = atomicrmw umin i16* @var16, i16 %offset acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i32:
+; CHECK-LABEL: test_atomic_load_umin_i32:
%old = atomicrmw umin i32* @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i64:
+; CHECK-LABEL: test_atomic_load_umin_i64:
%old = atomicrmw umin i64* @var64, i64 %offset acq_rel
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i8:
+; CHECK-LABEL: test_atomic_load_umax_i8:
%old = atomicrmw umax i8* @var8, i8 %offset acq_rel
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i16:
+; CHECK-LABEL: test_atomic_load_umax_i16:
%old = atomicrmw umax i16* @var16, i16 %offset monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i32:
+; CHECK-LABEL: test_atomic_load_umax_i32:
%old = atomicrmw umax i32* @var32, i32 %offset seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i64:
+; CHECK-LABEL: test_atomic_load_umax_i64:
%old = atomicrmw umax i64* @var64, i64 %offset release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i8:
+; CHECK-LABEL: test_atomic_cmpxchg_i8:
%old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i16:
+; CHECK-LABEL: test_atomic_cmpxchg_i16:
%old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
}
define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i32:
+; CHECK-LABEL: test_atomic_cmpxchg_i32:
%old = cmpxchg i32* @var32, i32 %wanted, i32 %new release
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
}
define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i64:
+; CHECK-LABEL: test_atomic_cmpxchg_i64:
%old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
}
define i8 @test_atomic_load_monotonic_i8() nounwind {
-; CHECK: test_atomic_load_monotonic_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_i8:
%val = load atomic i8* @var8 monotonic, align 1
; CHECK-NOT: dmb
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
}
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to i8*
}
define i8 @test_atomic_load_acquire_i8() nounwind {
-; CHECK: test_atomic_load_acquire_i8:
+; CHECK-LABEL: test_atomic_load_acquire_i8:
%val = load atomic i8* @var8 acquire, align 1
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
}
define i8 @test_atomic_load_seq_cst_i8() nounwind {
-; CHECK: test_atomic_load_seq_cst_i8:
+; CHECK-LABEL: test_atomic_load_seq_cst_i8:
%val = load atomic i8* @var8 seq_cst, align 1
; CHECK-NOT: dmb
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
}
define i16 @test_atomic_load_monotonic_i16() nounwind {
-; CHECK: test_atomic_load_monotonic_i16:
+; CHECK-LABEL: test_atomic_load_monotonic_i16:
%val = load atomic i16* @var16 monotonic, align 2
; CHECK-NOT: dmb
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
}
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to i32*
}
define i64 @test_atomic_load_seq_cst_i64() nounwind {
-; CHECK: test_atomic_load_seq_cst_i64:
+; CHECK-LABEL: test_atomic_load_seq_cst_i64:
%val = load atomic i64* @var64 seq_cst, align 8
; CHECK-NOT: dmb
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
}
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_i8:
store atomic i8 %val, i8* @var8 monotonic, align 1
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8]
}
define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to i8*
ret void
}
define void @test_atomic_store_release_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_release_i8:
+; CHECK-LABEL: test_atomic_store_release_i8:
store atomic i8 %val, i8* @var8 release, align 1
; CHECK-NOT: dmb
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
}
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_seq_cst_i8:
+; CHECK-LABEL: test_atomic_store_seq_cst_i8:
store atomic i8 %val, i8* @var8 seq_cst, align 1
; CHECK-NOT: dmb
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
}
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i16:
+; CHECK-LABEL: test_atomic_store_monotonic_i16:
store atomic i16 %val, i16* @var16 monotonic, align 2
; CHECK-NOT: dmb
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
}
define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to i32*
}
define void @test_atomic_store_release_i64(i64 %val) nounwind {
-; CHECK: test_atomic_store_release_i64:
+; CHECK-LABEL: test_atomic_store_release_i64:
store atomic i64 %val, i64* @var64 release, align 8
; CHECK-NOT: dmb
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
; it can relax it because it knows where get_func is. It can't!
; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func
; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func
-}
\ No newline at end of file
+}
store volatile i32 %combined, i32* %existing
ret void
-}
\ No newline at end of file
+}
}
define void @test_whole32(i32* %existing, i32* %new) {
-; CHECK: test_whole32:
+; CHECK-LABEL: test_whole32:
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
%oldval = load volatile i32* %existing
}
define void @test_whole64(i64* %existing, i64* %new) {
-; CHECK: test_whole64:
+; CHECK-LABEL: test_whole64:
; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
; CHECK-NOT: and
; CHECK: ret
}
define void @test_whole32_from64(i64* %existing, i64* %new) {
-; CHECK: test_whole32_from64:
+; CHECK-LABEL: test_whole32_from64:
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
; CHECK-NOT: and
; CHECK: ret
}
define void @test_32bit_masked(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_masked:
+; CHECK-LABEL: test_32bit_masked:
; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff
}
define void @test_64bit_masked(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_masked:
+; CHECK-LABEL: test_64bit_masked:
; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_complexmask:
+; CHECK-LABEL: test_32bit_complexmask:
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; Neither mask is is a contiguous set of 1s. BFI can't be used
define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_badmask:
+; CHECK-LABEL: test_32bit_badmask:
; CHECK-NOT: bfi
; CHECK: ret
; Ditto
define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_badmask:
+; CHECK-LABEL: test_64bit_badmask:
; CHECK-NOT: bfi
; CHECK: ret
; Bitfield insert where there's a left-over shr needed at the beginning
; (e.g. result of str.bf1 = str.bf2)
define void @test_32bit_with_shr(i32* %existing, i32* %new) {
-; CHECK: test_32bit_with_shr:
+; CHECK-LABEL: test_32bit_with_shr:
%oldval = load volatile i32* %existing
%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
@var64 = global i64 0
define void @test_extendb(i8 %var) {
-; CHECK: test_extendb:
+; CHECK-LABEL: test_extendb:
%sxt32 = sext i8 %var to i32
store volatile i32 %sxt32, i32* @var32
}
define void @test_extendh(i16 %var) {
-; CHECK: test_extendh:
+; CHECK-LABEL: test_extendh:
%sxt32 = sext i16 %var to i32
store volatile i32 %sxt32, i32* @var32
}
define void @test_extendw(i32 %var) {
-; CHECK: test_extendw:
+; CHECK-LABEL: test_extendw:
%sxt64 = sext i32 %var to i64
store volatile i64 %sxt64, i64* @var64
}
define void @test_shifts(i32 %val32, i64 %val64) {
-; CHECK: test_shifts:
+; CHECK-LABEL: test_shifts:
%shift1 = ashr i32 %val32, 31
store volatile i32 %shift1, i32* @var32
; LLVM can produce in-register extensions taking place entirely with
; 64-bit registers too.
define void @test_sext_inreg_64(i64 %in) {
-; CHECK: test_sext_inreg_64:
+; CHECK-LABEL: test_sext_inreg_64:
; i1 doesn't have an official alias, but crops up and is handled by
; the bitfield ops.
; These instructions don't actually select to official bitfield
; operations, but it's important that we select them somehow:
define void @test_zext_inreg_64(i64 %in) {
-; CHECK: test_zext_inreg_64:
+; CHECK-LABEL: test_zext_inreg_64:
%trunc_i8 = trunc i64 %in to i8
%zext_i8 = zext i8 %trunc_i8 to i64
}
define i64 @test_sext_inreg_from_32(i32 %in) {
-; CHECK: test_sext_inreg_from_32:
+; CHECK-LABEL: test_sext_inreg_from_32:
%small = trunc i32 %in to i1
%ext = sext i1 %small to i64
define i32 @test_ubfx32(i32* %addr) {
-; CHECK: test_ubfx32:
+; CHECK-LABEL: test_ubfx32:
; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
%fields = load i32* %addr
}
define i64 @test_ubfx64(i64* %addr) {
-; CHECK: test_ubfx64:
+; CHECK-LABEL: test_ubfx64:
; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
%fields = load i64* %addr
}
define i32 @test_sbfx32(i32* %addr) {
-; CHECK: test_sbfx32:
+; CHECK-LABEL: test_sbfx32:
; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
%fields = load i32* %addr
}
define i64 @test_sbfx64(i64* %addr) {
-; CHECK: test_sbfx64:
+; CHECK-LABEL: test_sbfx64:
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
%fields = load i64* %addr
@addr = global i8* null
define void @test_blockaddress() {
-; CHECK: test_blockaddress:
+; CHECK-LABEL: test_blockaddress:
store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
%val = load volatile i8** @addr
indirectbr i8* %val, [label %block]
end:
ret void
-}
\ No newline at end of file
+}
@var64 = global i64 0
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, i32 42, i32 52
}
define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
-; CHECK: test_floatcsel:
+; CHECK-LABEL: test_floatcsel:
%tst1 = fcmp one float %lhs32, %rhs32
; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinc:
+; CHECK-LABEL: test_csinc:
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
}
define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinv:
+; CHECK-LABEL: test_csinv:
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
}
define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csneg:
+; CHECK-LABEL: test_csneg:
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
}
define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_cset:
+; CHECK-LABEL: test_cset:
; N.b. code is not optimal here (32-bit csinc would be better) but
; incoming DAG is too complex
}
define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_csetm:
+; CHECK-LABEL: test_csetm:
%tst1 = icmp eq i32 %lhs, %rhs
%val1 = sext i1 %tst1 to i32
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
-; CHECK: test_select_i32:
+; CHECK-LABEL: test_select_i32:
%val = select i1 %bit, i32 %a, i32 %b
; CHECK: movz [[ONE:w[0-9]+]], #1
; CHECK: tst w0, [[ONE]]
}
define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
-; CHECK: test_select_i64:
+; CHECK-LABEL: test_select_i64:
%val = select i1 %bit, i64 %a, i64 %b
; CHECK: movz [[ONE:w[0-9]+]], #1
; CHECK: tst w0, [[ONE]]
}
define float @test_select_float(i1 %bit, float %a, float %b) {
-; CHECK: test_select_float:
+; CHECK-LABEL: test_select_float:
%val = select i1 %bit, float %a, float %b
; CHECK: movz [[ONE:w[0-9]+]], #1
; CHECK: tst w0, [[ONE]]
}
define double @test_select_double(i1 %bit, double %a, double %b) {
-; CHECK: test_select_double:
+; CHECK-LABEL: test_select_double:
%val = select i1 %bit, double %a, double %b
; CHECK: movz [[ONE:w[0-9]+]], #1
; CHECK: tst w0, [[ONE]]
}
define i32 @test_brcond(i1 %bit) {
-; CHECK: test_brcond:
+; CHECK-LABEL: test_brcond:
br i1 %bit, label %true, label %false
; CHECK: tbz {{w[0-9]+}}, #0, .LBB
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_madd32:
+; CHECK-LABEL: test_madd32:
%mid = mul i32 %val1, %val2
%res = add i32 %val0, %mid
; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
}
define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_madd64:
+; CHECK-LABEL: test_madd64:
%mid = mul i64 %val1, %val2
%res = add i64 %val0, %mid
; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
}
define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_msub32:
+; CHECK-LABEL: test_msub32:
%mid = mul i32 %val1, %val2
%res = sub i32 %val0, %mid
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
}
define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_msub64:
+; CHECK-LABEL: test_msub64:
%mid = mul i64 %val1, %val2
%res = sub i64 %val0, %mid
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
}
define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smaddl:
+; CHECK-LABEL: test_smaddl:
%ext1 = sext i32 %val1 to i64
%ext2 = sext i32 %val2 to i64
%prod = mul i64 %ext1, %ext2
}
define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smsubl:
+; CHECK-LABEL: test_smsubl:
%ext1 = sext i32 %val1 to i64
%ext2 = sext i32 %val2 to i64
%prod = mul i64 %ext1, %ext2
}
define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umaddl:
+; CHECK-LABEL: test_umaddl:
%ext1 = zext i32 %val1 to i64
%ext2 = zext i32 %val2 to i64
%prod = mul i64 %ext1, %ext2
}
define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umsubl:
+; CHECK-LABEL: test_umsubl:
%ext1 = zext i32 %val1 to i64
%ext2 = zext i32 %val2 to i64
%prod = mul i64 %ext1, %ext2
}
define i64 @test_smulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_smulh:
+; CHECK-LABEL: test_smulh:
%ext1 = sext i64 %lhs to i128
%ext2 = sext i64 %rhs to i128
%res = mul i128 %ext1, %ext2
}
define i64 @test_umulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_umulh:
+; CHECK-LABEL: test_umulh:
%ext1 = zext i64 %lhs to i128
%ext2 = zext i64 %rhs to i128
%res = mul i128 %ext1, %ext2
}
define i32 @test_mul32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mul32:
+; CHECK-LABEL: test_mul32:
%res = mul i32 %lhs, %rhs
; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
ret i32 %res
}
define i64 @test_mul64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mul64:
+; CHECK-LABEL: test_mul64:
%res = mul i64 %lhs, %rhs
; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
ret i64 %res
}
define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mneg32:
+; CHECK-LABEL: test_mneg32:
%prod = mul i32 %lhs, %rhs
%res = sub i32 0, %prod
; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
}
define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mneg64:
+; CHECK-LABEL: test_mneg64:
%prod = mul i64 %lhs, %rhs
%res = sub i64 0, %prod
; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
}
define i64 @test_smull(i32 %lhs, i32 %rhs) {
-; CHECK: test_smull:
+; CHECK-LABEL: test_smull:
%ext1 = sext i32 %lhs to i64
%ext2 = sext i32 %rhs to i64
%res = mul i64 %ext1, %ext2
}
define i64 @test_umull(i32 %lhs, i32 %rhs) {
-; CHECK: test_umull:
+; CHECK-LABEL: test_umull:
%ext1 = zext i32 %lhs to i64
%ext2 = zext i32 %rhs to i64
%res = mul i64 %ext1, %ext2
}
define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_smnegl:
+; CHECK-LABEL: test_smnegl:
%ext1 = sext i32 %lhs to i64
%ext2 = sext i32 %rhs to i64
%prod = mul i64 %ext1, %ext2
}
define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_umnegl:
+; CHECK-LABEL: test_umnegl:
%ext1 = zext i32 %lhs to i64
%ext2 = zext i32 %rhs to i64
%prod = mul i64 %ext1, %ext2
; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
define i32 @test_lsl32() {
-; CHECK: test_lsl32:
+; CHECK-LABEL: test_lsl32:
%val = load i32* @var32_0
%ret = shl i32 1, %val
}
define i32 @test_lsr32() {
-; CHECK: test_lsr32:
+; CHECK-LABEL: test_lsr32:
%val = load i32* @var32_0
%ret = lshr i32 1, %val
}
define i32 @test_asr32(i32 %in) {
-; CHECK: test_asr32:
+; CHECK-LABEL: test_asr32:
%val = load i32* @var32_0
%ret = ashr i32 %in, %val
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
-}
\ No newline at end of file
+}
declare void @bar(i32)
define void @test_float(float %a, float %b) {
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
%tst1 = fcmp oeq float %a, %b
br i1 %tst1, label %end, label %t2
}
define void @test_double(double %a, double %b) {
-; CHECK: test_double:
+; CHECK-LABEL: test_double:
%tst1 = fcmp oeq double %a, %b
br i1 %tst1, label %end, label %t2
@var64 = global i64 0
define void @test_fcvtzs(float %flt, double %dbl) {
-; CHECK: test_fcvtzs:
+; CHECK-LABEL: test_fcvtzs:
%fix1 = fmul float %flt, 128.0
%cvt1 = fptosi float %fix1 to i32
}
define void @test_fcvtzu(float %flt, double %dbl) {
-; CHECK: test_fcvtzu:
+; CHECK-LABEL: test_fcvtzu:
%fix1 = fmul float %flt, 128.0
%cvt1 = fptoui float %fix1 to i32
@vardouble = global double 0.0
define void @test_scvtf(i32 %int, i64 %long) {
-; CHECK: test_scvtf:
+; CHECK-LABEL: test_scvtf:
%cvt1 = sitofp i32 %int to float
%fix1 = fdiv float %cvt1, 128.0
}
define void @test_ucvtf(i32 %int, i64 %long) {
-; CHECK: test_ucvtf:
+; CHECK-LABEL: test_ucvtf:
%cvt1 = uitofp i32 %int to float
%fix1 = fdiv float %cvt1, 128.0
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i32 @test_floattoi32(float %in) {
-; CHECK: test_floattoi32:
+; CHECK-LABEL: test_floattoi32:
%signed = fptosi float %in to i32
%unsigned = fptoui float %in to i32
}
define i32 @test_doubletoi32(double %in) {
-; CHECK: test_doubletoi32:
+; CHECK-LABEL: test_doubletoi32:
%signed = fptosi double %in to i32
%unsigned = fptoui double %in to i32
}
define i64 @test_floattoi64(float %in) {
-; CHECK: test_floattoi64:
+; CHECK-LABEL: test_floattoi64:
%signed = fptosi float %in to i64
%unsigned = fptoui float %in to i64
}
define i64 @test_doubletoi64(double %in) {
-; CHECK: test_doubletoi64:
+; CHECK-LABEL: test_doubletoi64:
%signed = fptosi double %in to i64
%unsigned = fptoui double %in to i64
}
define float @test_i32tofloat(i32 %in) {
-; CHECK: test_i32tofloat:
+; CHECK-LABEL: test_i32tofloat:
%signed = sitofp i32 %in to float
%unsigned = uitofp i32 %in to float
}
define double @test_i32todouble(i32 %in) {
-; CHECK: test_i32todouble:
+; CHECK-LABEL: test_i32todouble:
%signed = sitofp i32 %in to double
%unsigned = uitofp i32 %in to double
}
define float @test_i64tofloat(i64 %in) {
-; CHECK: test_i64tofloat:
+; CHECK-LABEL: test_i64tofloat:
%signed = sitofp i64 %in to float
%unsigned = uitofp i64 %in to float
}
define double @test_i64todouble(i64 %in) {
-; CHECK: test_i64todouble:
+; CHECK-LABEL: test_i64todouble:
%signed = sitofp i64 %in to double
%unsigned = uitofp i64 %in to double
}
define i32 @test_bitcastfloattoi32(float %in) {
-; CHECK: test_bitcastfloattoi32:
+; CHECK-LABEL: test_bitcastfloattoi32:
%res = bitcast float %in to i32
; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
}
define i64 @test_bitcastdoubletoi64(double %in) {
-; CHECK: test_bitcastdoubletoi64:
+; CHECK-LABEL: test_bitcastdoubletoi64:
%res = bitcast double %in to i64
; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
}
define float @test_bitcasti32tofloat(i32 %in) {
-; CHECK: test_bitcasti32tofloat:
+; CHECK-LABEL: test_bitcasti32tofloat:
%res = bitcast i32 %in to float
; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
}
define double @test_bitcasti64todouble(i64 %in) {
-; CHECK: test_bitcasti64todouble:
+; CHECK-LABEL: test_bitcasti64todouble:
%res = bitcast i64 %in to double
; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
@var = global i32 0
define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
-; CHECK: test_multiflag:
+; CHECK-LABEL: test_multiflag:
%test = icmp ne i32 %n, %m
; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
@vardouble = global double 0.0
define void @testfloat() {
-; CHECK: testfloat:
+; CHECK-LABEL: testfloat:
%val1 = load float* @varfloat
%val2 = fadd float %val1, %val1
}
define void @testdouble() {
-; CHECK: testdouble:
+; CHECK-LABEL: testdouble:
%val1 = load double* @vardouble
%val2 = fadd double %val1, %val1
@vardouble = global double 0.0
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float 0.0, float 1.0
}
define double @testd_fmadd(double %a, double %b, double %c) {
-; CHECK: testd_fmadd:
+; CHECK-LABEL: testd_fmadd:
; CHECK-NOFAST: testd_fmadd:
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
}
define double @testd_fmsub(double %a, double %b, double %c) {
-; CHECK: testd_fmsub:
+; CHECK-LABEL: testd_fmsub:
; CHECK-NOFAST: testd_fmsub:
%nega = fsub double -0.0, %a
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
}
define double @testd_fnmadd(double %a, double %b, double %c) {
-; CHECK: testd_fnmadd:
+; CHECK-LABEL: testd_fnmadd:
; CHECK-NOFAST: testd_fnmadd:
%negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
}
define double @testd_fnmsub(double %a, double %b, double %c) {
-; CHECK: testd_fnmsub:
+; CHECK-LABEL: testd_fnmsub:
; CHECK-NOFAST: testd_fnmsub:
%nega = fsub double -0.0, %a
%negc = fsub double -0.0, %c
; which is not supported.
define fp128 @test_folding() {
-; CHECK: test_folding:
+; CHECK-LABEL: test_folding:
%l = alloca i32
store i32 42, i32* %l
%val = load i32* %l
; successfully.
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
ret fp128 %fpval
-}
\ No newline at end of file
+}
@rhs = global fp128 zeroinitializer
define fp128 @test_add() {
-; CHECK: test_add:
+; CHECK-LABEL: test_add:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define fp128 @test_sub() {
-; CHECK: test_sub:
+; CHECK-LABEL: test_sub:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define fp128 @test_mul() {
-; CHECK: test_mul:
+; CHECK-LABEL: test_mul:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define fp128 @test_div() {
-; CHECK: test_div:
+; CHECK-LABEL: test_div:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
@var64 = global i64 0
define void @test_fptosi() {
-; CHECK: test_fptosi:
+; CHECK-LABEL: test_fptosi:
%val = load fp128* @lhs
%val32 = fptosi fp128 %val to i32
}
define void @test_fptoui() {
-; CHECK: test_fptoui:
+; CHECK-LABEL: test_fptoui:
%val = load fp128* @lhs
%val32 = fptoui fp128 %val to i32
}
define void @test_sitofp() {
-; CHECK: test_sitofp:
+; CHECK-LABEL: test_sitofp:
%src32 = load i32* @var32
%val32 = sitofp i32 %src32 to fp128
}
define void @test_uitofp() {
-; CHECK: test_uitofp:
+; CHECK-LABEL: test_uitofp:
%src32 = load i32* @var32
%val32 = uitofp i32 %src32 to fp128
}
define i1 @test_setcc1() {
-; CHECK: test_setcc1:
+; CHECK-LABEL: test_setcc1:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define i1 @test_setcc2() {
-; CHECK: test_setcc2:
+; CHECK-LABEL: test_setcc2:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define i32 @test_br_cc() {
-; CHECK: test_br_cc:
+; CHECK-LABEL: test_br_cc:
%lhs = load fp128* @lhs
%rhs = load fp128* @rhs
}
define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
store fp128 %val, fp128* @lhs
@vardouble = global double 0.0
define void @test_round() {
-; CHECK: test_round:
+; CHECK-LABEL: test_round:
%val = load fp128* @lhs
}
define void @test_extend() {
-; CHECK: test_extend:
+; CHECK-LABEL: test_extend:
%val = load fp128* @lhs
; Make sure the weird hex constant below *is* -0.0
; CHECK-NEXT: fp128 -0
-; CHECK: test_neg:
+; CHECK-LABEL: test_neg:
; Could in principle be optimized to fneg which we can't select, this makes
; sure that doesn't happen.
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
define i32 @test_extern() {
-; CHECK: test_extern:
+; CHECK-LABEL: test_extern:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
; CHECK: bl memcpy
ret i32 0
@var32_align64 = global [3 x i32] zeroinitializer, align 8
define i64 @test_align32() {
-; CHECK: test_align32:
+; CHECK-LABEL: test_align32:
%addr = bitcast [3 x i32]* @var32 to i64*
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
}
define i64 @test_align64() {
-; CHECK: test_align64:
+; CHECK-LABEL: test_align64:
%addr = bitcast [3 x i64]* @var64 to i64*
; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
}
define i64 @test_var32_align64() {
-; CHECK: test_var32_align64:
+; CHECK-LABEL: test_var32_align64:
%addr = bitcast [3 x i32]* @var32_align64 to i64*
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
@yet_another_var = external global {i32, i32}
define i64 @test_yet_another_var() {
-; CHECK: test_yet_another_var:
+; CHECK-LABEL: test_yet_another_var:
; @yet_another_var has a preferred alignment of 8, but that's not enough if
; we're going to be linking against other things. Its ABI alignment is only 4
}
define i64()* @test_functions() {
-; CHECK: test_functions:
+; CHECK-LABEL: test_functions:
ret i64()* @test_yet_another_var
; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var
%diff = sub i64 %endi, %starti
ret i64 %diff
; CHECK: movz x0, #16
-}
\ No newline at end of file
+}
@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
-; CHECK: .section .init_array
\ No newline at end of file
+; CHECK: .section .init_array
; Out of range immediate for I.
call void asm sideeffect "add x0, x0, $0", "I"(i32 4096)
ret void
-}
\ No newline at end of file
+}
; 32-bit bitpattern ending in 1101 can't be produced.
call void asm sideeffect "and w0, w0, $0", "K"(i32 13)
ret void
-}
\ No newline at end of file
+}
; 32-bit bitpattern ending in 1101 can't be produced.
call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296)
ret void
-}
\ No newline at end of file
+}
; 32-bit bitpattern ending in 1101 can't be produced.
call void asm sideeffect "and x0, x0, $0", "L"(i32 13)
ret void
-}
\ No newline at end of file
+}
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r:
+; CHECK-LABEL: test_inline_constraint_r:
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
ret i64 %val
}
define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
-; CHECK: test_small_reg:
+; CHECK-LABEL: test_small_reg:
%val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
ret i16 %val
}
define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r_imm:
+; CHECK-LABEL: test_inline_constraint_r_imm:
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
; CHECK: movz [[FOUR:x[0-9]+]], #4
; CHECK: movz [[TWELVE:w[0-9]+]], #12
; m is permitted to have a base/offset form. We don't do that
; currently though.
define i32 @test_inline_constraint_m(i32 *%ptr) {
-; CHECK: test_inline_constraint_m:
+; CHECK-LABEL: test_inline_constraint_m:
%val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
ret i32 %val
; Q should *never* have base/offset form even if given the chance.
define i32 @test_inline_constraint_Q(i32 *%ptr) {
-; CHECK: test_inline_constraint_Q:
+; CHECK-LABEL: test_inline_constraint_Q:
%val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
ret i32 %val
@dump = global fp128 zeroinitializer
define void @test_inline_constraint_I() {
-; CHECK: test_inline_constraint_I:
+; CHECK-LABEL: test_inline_constraint_I:
call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
; CHECK: add x0, x0, #0
; Skip J because it's useless
define void @test_inline_constraint_K() {
-; CHECK: test_inline_constraint_K:
+; CHECK-LABEL: test_inline_constraint_K:
call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
; CHECK: and w0, w0, #-1431655766
}
define void @test_inline_constraint_L() {
-; CHECK: test_inline_constraint_L:
+; CHECK-LABEL: test_inline_constraint_L:
call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
; CHECK: and x0, x0, #4294967296
@var = global i32 0
define void @test_inline_constraint_S() {
-; CHECK: test_inline_constraint_S:
+; CHECK-LABEL: test_inline_constraint_S:
call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
}
define i32 @test_inline_constraint_S_label(i1 %in) {
-; CHECK: test_inline_constraint_S_label:
+; CHECK-LABEL: test_inline_constraint_S_label:
call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
; CHECK: adr x0, .Ltmp{{[0-9]+}}
br i1 %in, label %loc, label %loc2
}
define void @test_inline_constraint_Y() {
-; CHECK: test_inline_constraint_Y:
+; CHECK-LABEL: test_inline_constraint_Y:
call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
; CHECK: fcmp s0, #0.0
ret void
}
define void @test_inline_constraint_Z() {
-; CHECK: test_inline_constraint_Z:
+; CHECK-LABEL: test_inline_constraint_Z:
call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
; CHECK: cmp w0, #0
ret void
-}
\ No newline at end of file
+}
@var_tlsle = thread_local(localexec) global i32 0
define void @test_inline_modifier_L() nounwind {
-; CHECK: test_inline_modifier_L:
+; CHECK-LABEL: test_inline_modifier_L:
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple)
call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd)
}
define void @test_inline_modifier_G() nounwind {
-; CHECK: test_inline_modifier_G:
+; CHECK-LABEL: test_inline_modifier_G:
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld)
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle)
; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
}
define void @test_inline_modifier_A() nounwind {
-; CHECK: test_inline_modifier_A:
+; CHECK-LABEL: test_inline_modifier_A:
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple)
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got)
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd)
}
define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
-; CHECK: test_inline_modifier_wx:
+; CHECK-LABEL: test_inline_modifier_wx:
call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small)
call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small)
call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small)
}
define void @test_inline_modifier_bhsdq() nounwind {
-; CHECK: test_inline_modifier_bhsdq:
+; CHECK-LABEL: test_inline_modifier_bhsdq:
call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
}
define void @test_inline_modifier_c() nounwind {
-; CHECK: test_inline_modifier_c:
+; CHECK-LABEL: test_inline_modifier_c:
call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3)
; CHECK: adr x0, 3
ret void
-}
\ No newline at end of file
+}
@addr = global i8* null
define void @test_bigframe() {
-; CHECK: test_bigframe:
+; CHECK-LABEL: test_bigframe:
; CHECK: .cfi_startproc
%var1 = alloca i8, i32 20000000
}
define void @test_mediumframe() {
-; CHECK: test_mediumframe:
+; CHECK-LABEL: test_mediumframe:
%var1 = alloca i8, i32 1000000
%var2 = alloca i8, i32 16
%var3 = alloca i8, i32 1000000
; If temporary registers are allocated for adjustment, they should *not* clobber
; argument registers.
define void @test_tempallocation([8 x i64] %val) nounwind {
-; CHECK: test_tempallocation:
+; CHECK-LABEL: test_tempallocation:
%var = alloca i8, i32 1000000
; CHECK: sub sp, sp,
@var64 = global i64 0
define void @test_and(i32 %in32, i64 %in64) {
-; CHECK: test_and:
+; CHECK-LABEL: test_and:
%val0 = and i32 %in32, 2863311530
store volatile i32 %val0, i32* @var32
}
define void @test_orr(i32 %in32, i64 %in64) {
-; CHECK: test_orr:
+; CHECK-LABEL: test_orr:
%val0 = or i32 %in32, 2863311530
store volatile i32 %val0, i32* @var32
}
define void @test_eor(i32 %in32, i64 %in64) {
-; CHECK: test_eor:
+; CHECK-LABEL: test_eor:
%val0 = xor i32 %in32, 2863311530
store volatile i32 %val0, i32* @var32
}
define void @test_mov(i32 %in32, i64 %in64) {
-; CHECK: test_mov:
+; CHECK-LABEL: test_mov:
%val0 = add i32 %in32, 2863311530
store i32 %val0, i32* @var32
; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i64 @test0() {
-; CHECK: test0:
+; CHECK-LABEL: test0:
; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
; CHECK: mov x0, xzr
ret i64 0
}
define i64 @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movz x0, #1
ret i64 1
}
define i64 @test2() {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movz x0, #65535
ret i64 65535
}
define i64 @test3() {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movz x0, #1, lsl #16
ret i64 65536
}
define i64 @test4() {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movz x0, #65535, lsl #16
ret i64 4294901760
}
define i64 @test5() {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: movz x0, #1, lsl #32
ret i64 4294967296
}
define i64 @test6() {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: movz x0, #65535, lsl #32
ret i64 281470681743360
}
define i64 @test7() {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: movz x0, #1, lsl #48
ret i64 281474976710656
}
; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
; couldn't. Useful even for i64
define i64 @test8() {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: movn w0, #60875
ret i64 4294906420
}
define i64 @test9() {
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: movn x0, #0
ret i64 -1
}
define i64 @test10() {
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: movn x0, #60875, lsl #16
ret i64 18446744069720047615
}
@var32 = global i32 0
define void @test11() {
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: mov {{w[0-9]+}}, wzr
store i32 0, i32* @var32
ret void
}
define void @test12() {
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: movz {{w[0-9]+}}, #1
store i32 1, i32* @var32
ret void
}
define void @test13() {
-; CHECK: test13:
+; CHECK-LABEL: test13:
; CHECK: movz {{w[0-9]+}}, #65535
store i32 65535, i32* @var32
ret void
}
define void @test14() {
-; CHECK: test14:
+; CHECK-LABEL: test14:
; CHECK: movz {{w[0-9]+}}, #1, lsl #16
store i32 65536, i32* @var32
ret void
}
define void @test15() {
-; CHECK: test15:
+; CHECK-LABEL: test15:
; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
store i32 4294901760, i32* @var32
ret void
}
define void @test16() {
-; CHECK: test16:
+; CHECK-LABEL: test16:
; CHECK: movn {{w[0-9]+}}, #0
store i32 -1, i32* @var32
ret void
}
define i64 @test17() {
-; CHECK: test17:
+; CHECK-LABEL: test17:
; Mustn't MOVN w0 here.
; CHECK: movn x0, #2
declare i8* @__cxa_begin_catch(i8*)
-declare void @__cxa_end_catch()
\ No newline at end of file
+declare void @__cxa_end_catch()
; actually capable of that (the test was omitted from LowerFormalArguments).
define void @test_bitcast_lower(<2 x i32> %a) {
-; CHECK: test_bitcast_lower:
+; CHECK-LABEL: test_bitcast_lower:
ret void
; CHECK: ret
tail call void %func()
; CHECK: br {{x([0-79]|1[0-8])}}
ret void
-}
\ No newline at end of file
+}
declare void @bar(i8*)
define i64 @test_chains() {
-; CHECK: test_chains:
+; CHECK-LABEL: test_chains:
%locvar = alloca i8
declare void @bar()
define void @test_w29_reserved() {
-; CHECK: test_w29_reserved:
+; CHECK-LABEL: test_w29_reserved:
; CHECK: .cfi_startproc
; CHECK: .cfi_def_cfa sp, 96
; CHECK: add x29, sp, #{{[0-9]+}}
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64)
define i64 @test_select(i64 %lhs, i64 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
%res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs)
%flag = extractvalue {i64, i1} %res, 1
%retval = select i1 %flag, i64 %lhs, i64 %rhs
ret i64 %retval
; CHECK: ret
-}
\ No newline at end of file
+}
declare fp128 @sinl(fp128) readonly
declare float @cosf(float) readonly
declare double @cos(double) readonly
-declare fp128 @cosl(fp128) readonly
\ No newline at end of file
+declare fp128 @cosl(fp128) readonly
@general_dynamic_var = external thread_local global i32
define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
%val = load i32* @general_dynamic_var
ret i32 %val
@general_dynamic_var = external thread_local global i32
define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
%val = load i32* @general_dynamic_var
ret i32 %val
}
define i32* @test_generaldynamic_addr() {
-; CHECK: test_generaldynamic_addr:
+; CHECK-LABEL: test_generaldynamic_addr:
ret i32* @general_dynamic_var
@local_dynamic_var = external thread_local(localdynamic) global i32
define i32 @test_localdynamic() {
-; CHECK: test_localdynamic:
+; CHECK-LABEL: test_localdynamic:
%val = load i32* @local_dynamic_var
ret i32 %val
}
define i32* @test_localdynamic_addr() {
-; CHECK: test_localdynamic_addr:
+; CHECK-LABEL: test_localdynamic_addr:
ret i32* @local_dynamic_var
@local_dynamic_var2 = external thread_local(localdynamic) global i32
define i32 @test_localdynamic_deduplicate() {
-; CHECK: test_localdynamic_deduplicate:
+; CHECK-LABEL: test_localdynamic_deduplicate:
%val = load i32* @local_dynamic_var
%val2 = load i32* @local_dynamic_var2
@initial_exec_var = external thread_local(initialexec) global i32
define i32 @test_initial_exec() {
-; CHECK: test_initial_exec:
+; CHECK-LABEL: test_initial_exec:
%val = load i32* @initial_exec_var
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
}
define i32* @test_initial_exec_addr() {
-; CHECK: test_initial_exec_addr:
+; CHECK-LABEL: test_initial_exec_addr:
ret i32* @initial_exec_var
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
@local_exec_var = thread_local(initialexec) global i32 0
define i32 @test_local_exec() {
-; CHECK: test_local_exec:
+; CHECK-LABEL: test_local_exec:
%val = load i32* @local_exec_var
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
}
define i32* @test_local_exec_addr() {
-; CHECK: test_local_exec_addr:
+; CHECK-LABEL: test_local_exec_addr:
ret i32* @local_exec_var
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
@var64 = global i64 0
define i32 @test_tbz() {
-; CHECK: test_tbz:
+; CHECK-LABEL: test_tbz:
%val = load i32* @var32
%val64 = load i64* @var64
declare void @llvm.va_start(i8*)
define void @test_simple(i32 %n, ...) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
; CHECK: str q7, [x[[FPRBASE]], #112]
}
define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
-; CHECK: test_fewargs:
+; CHECK-LABEL: test_fewargs:
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
; CHECK: str q7, [x[[FPRBASE]], #96]
}
define void @test_nospare([8 x i64], [8 x float], ...) {
-; CHECK: test_nospare:
+; CHECK-LABEL: test_nospare:
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_start(i8* %addr)
; If there are non-variadic arguments on the stack (here two i64s) then the
; __stack field should point just past them.
define void @test_offsetstack([10 x i64], [3 x float], ...) {
-; CHECK: test_offsetstack:
+; CHECK-LABEL: test_offsetstack:
; CHECK: sub sp, sp, #80
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
; CHECK: str q7, [x[[FPRBASE]], #64]
declare void @llvm.va_end(i8*)
define void @test_va_end() nounwind {
-; CHECK: test_va_end:
+; CHECK-LABEL: test_va_end:
; CHECK-NEXT: BB#0
%addr = bitcast %va_list* @var to i8*
@second_list = global %va_list zeroinitializer
define void @test_va_copy() {
-; CHECK: test_va_copy:
+; CHECK-LABEL: test_va_copy:
%srcaddr = bitcast %va_list* @var to i8*
%dstaddr = bitcast %va_list* @second_list to i8*
call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
@var64 = global i64 0
define void @test_zr() {
-; CHECK: test_zr:
+; CHECK-LABEL: test_zr:
store i32 0, i32* @var32
; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
}
define void @test_sp(i32 %val) {
-; CHECK: test_sp:
+; CHECK-LABEL: test_sp:
; Important correctness point here is that LLVM doesn't try to use xzr
; as an addressing register: "str w0, [xzr]" is not a valid A64
ret void
; CHECK: ret
-}
\ No newline at end of file
+}
define i32 @test() nounwind optsize ssp {
entry:
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: push
; CHECK-NOT: push
%block_size = alloca i32, align 4
@i8_src2 = global <2 x i8> <i8 2, i8 1>
define void @test_neon_vector_add_2xi8() nounwind {
-; CHECK: test_neon_vector_add_2xi8:
+; CHECK-LABEL: test_neon_vector_add_2xi8:
%1 = load <2 x i8>* @i8_src1
%2 = load <2 x i8>* @i8_src2
%3 = add <2 x i8> %1, %2
}
define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
-; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
+; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
%1 = load volatile <2 x i8>* @i8_src1
%2 = load volatile <2 x i8>* @i8_src2
%3 = ashr <2 x i8> %1, %2
declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
define void @test_neon_call_return_v2i16() {
-; CHECK: test_neon_call_return_v2i16:
+; CHECK-LABEL: test_neon_call_return_v2i16:
%1 = load <2 x i16>* @src1_v2i16
%2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
store <2 x i16> %2, <2 x i16>* @res_v2i16
define void @test_sqrt(<4 x float>* %X) nounwind {
-; CHECK: test_sqrt:
+; CHECK-LABEL: test_sqrt:
; CHECK: movw r1, :lower16:{{.*}}
; CHECK: movt r1, :upper16:{{.*}}
define void @test_cos(<4 x float>* %X) nounwind {
-; CHECK: test_cos:
+; CHECK-LABEL: test_cos:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_exp(<4 x float>* %X) nounwind {
-; CHECK: test_exp:
+; CHECK-LABEL: test_exp:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_exp2(<4 x float>* %X) nounwind {
-; CHECK: test_exp2:
+; CHECK-LABEL: test_exp2:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_log10(<4 x float>* %X) nounwind {
-; CHECK: test_log10:
+; CHECK-LABEL: test_log10:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_log(<4 x float>* %X) nounwind {
-; CHECK: test_log:
+; CHECK-LABEL: test_log:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_log2(<4 x float>* %X) nounwind {
-; CHECK: test_log2:
+; CHECK-LABEL: test_log2:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_pow(<4 x float>* %X) nounwind {
-; CHECK: test_pow:
+; CHECK-LABEL: test_pow:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_powi(<4 x float>* %X) nounwind {
-; CHECK: test_powi:
+; CHECK-LABEL: test_powi:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_sin(<4 x float>* %X) nounwind {
-; CHECK: test_sin:
+; CHECK-LABEL: test_sin:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
define void @test_floor(<4 x float>* %X) nounwind {
-; CHECK: test_floor:
+; CHECK-LABEL: test_floor:
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
@var_v2i64 = global <2 x i64> zeroinitializer
define void @test_v2i8tov2i32() {
-; CHECK: test_v2i8tov2i32:
+; CHECK-LABEL: test_v2i8tov2i32:
%i8val = load <2 x i8>* @var_v2i8
}
define void @test_v2i8tov2i64() {
-; CHECK: test_v2i8tov2i64:
+; CHECK-LABEL: test_v2i8tov2i64:
%i8val = load <2 x i8>* @var_v2i8
}
define void @test_v4i8tov4i16() {
-; CHECK: test_v4i8tov4i16:
+; CHECK-LABEL: test_v4i8tov4i16:
%i8val = load <4 x i8>* @var_v4i8
}
define void @test_v4i8tov4i32() {
-; CHECK: test_v4i8tov4i32:
+; CHECK-LABEL: test_v4i8tov4i32:
%i8val = load <4 x i8>* @var_v4i8
}
define void @test_v2i16tov2i32() {
-; CHECK: test_v2i16tov2i32:
+; CHECK-LABEL: test_v2i16tov2i32:
%i16val = load <2 x i16>* @var_v2i16
}
define void @test_v2i16tov2i64() {
-; CHECK: test_v2i16tov2i64:
+; CHECK-LABEL: test_v2i16tov2i64:
%i16val = load <2 x i16>* @var_v2i16
declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind
-; CHECK: test_byval_8_bytes_alignment:
+; CHECK-LABEL: test_byval_8_bytes_alignment:
define void @test_byval_8_bytes_alignment(i32 %i, ...) {
entry:
; CHECK: stm r0, {r1, r2, r3}
declare void @f(double);
-; CHECK: test_byval_8_bytes_alignment_fixed_arg:
+; CHECK-LABEL: test_byval_8_bytes_alignment_fixed_arg:
; CHECK-NOT: str r1
; CHECK: str r3, [sp, #12]
; CHECK: str r2, [sp, #8]
declare i32 @printf(i8*, ...)
-; CHECK: test_byval_usage_scheduling:
+; CHECK-LABEL: test_byval_usage_scheduling:
; CHECK: str r3, [sp, #12]
; CHECK: str r2, [sp, #8]
; CHECK: vldr d16, [sp, #8]
; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
define i64 @test1(i64* %ptr, i64 %val) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
}
define i64 @test2(i64* %ptr, i64 %val) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
}
define i64 @test3(i64* %ptr, i64 %val) {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
}
define i64 @test4(i64* %ptr, i64 %val) {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
}
define i64 @test5(i64* %ptr, i64 %val) {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
}
define i64 @test6(i64* %ptr, i64 %val) {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
}
define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: cmp [[REG1]]
; Compiles down to cmpxchg
; FIXME: Should compile to a single ldrexd
define i64 @test8(i64* %ptr) {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: cmp [[REG1]]
; CHECK: cmpeq [[REG2]]
; Compiles down to atomicrmw xchg; there really isn't any more efficient
; way to write it.
define void @test9(i64* %ptr, i64 %val) {
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
}
define i64 @test10(i64* %ptr, i64 %val) {
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
}
define i64 @test11(i64* %ptr, i64 %val) {
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
}
define i64 @test12(i64* %ptr, i64 %val) {
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
}
define i64 @test13(i64* %ptr, i64 %val) {
-; CHECK: test13:
+; CHECK-LABEL: test13:
; CHECK: dmb {{ish$}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
%z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
call void @g(<16 x i8> %z)
ret void
-}
\ No newline at end of file
+}
; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
; PR15525
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2
; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to0:
%vec = insertelement <2 x float> %in, float %arg, i32 0
%res = fadd <2 x float> %vec, %vec
}
define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to1:
%vec = insertelement <2 x float> %in, float %arg, i32 1
%res = fadd <2 x float> %vec, %vec
}
define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to0:
%vec = insertelement <2 x float> %in, float %arg, i32 0
%res = fadd <2 x float> %vec, %vec
}
define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to1:
%vec = insertelement <2 x float> %in, float %arg, i32 1
%res = fadd <2 x float> %vec, %vec
define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
-; CHECK: test_vmovs_via_vdup:
+; CHECK-LABEL: test_vmovs_via_vdup:
; Do an operation (which will end up NEON because of +neonfp) to convince the
; execution-domain pass that NEON is a good thing to use.
; This is a comp
define float @test_ineligible(float, float %in) {
-; CHECK: test_ineligible:
+; CHECK-LABEL: test_ineligible:
%sqrt = call float @llvm.sqrt.f32(float %in)
%val = fadd float %sqrt, %sqrt
}
define i32 @test_vmovs_no_sreg(i32 %in) {
-; CHECK: test_vmovs_no_sreg:
+; CHECK-LABEL: test_vmovs_no_sreg:
; Check that the movement to and from GPRs takes place in the NEON domain.
; CHECK: vmov.32 d
; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: vabs.f32 q0, q0
define <4 x float> @test(<4 x float> %a) {
%foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
}
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: vabs.f32 d0, d0
define <2 x float> @test2(<2 x float> %a) {
%foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
declare float @fabsf(float)
-; VFP2: test:
+; VFP2-LABEL: test:
; VFP2: vabs.f32 s
-; NFP1: test:
+; NFP1-LABEL: test:
; NFP1: vabs.f32 d
-; NFP0: test:
+; NFP0-LABEL: test:
; NFP0: vabs.f32 s
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
ret float %0
}
-; VFP2: test:
+; VFP2-LABEL: test:
; VFP2: vadd.f32 s
-; NFP1: test:
+; NFP1-LABEL: test:
; NFP1: vadd.f32 d
-; NFP0: test:
+; NFP0-LABEL: test:
; NFP0: vadd.f32 s
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
; CORTEXA8: vadd.f32 s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
; CORTEXA8U: vadd.f32 d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
; CORTEXA9: vadd.f32 s
if.end: ; preds = %if.then, %entry
ret void
-; ARM: test1:
+; ARM-LABEL: test1:
; ARM: tst r0, #1
-; THUMB: test1:
+; THUMB-LABEL: test1:
; THUMB: tst.w r0, #1
}
; Check some simple operations with immediates
define void @test2(i32 %tmp, i32* %ptr) nounwind {
-; THUMB: test2:
-; ARM: test2:
+; THUMB-LABEL: test2:
+; ARM-LABEL: test2:
b1:
%a = add i32 %tmp, 4096
}
define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
-; THUMB: test3:
-; ARM: test3:
+; THUMB-LABEL: test3:
+; ARM-LABEL: test3:
bb1:
%a1 = trunc i32 %tmp to i16
; rdar://8984306
define float @test1(float %x, float %y) nounwind {
entry:
-; SOFT: test1:
+; SOFT-LABEL: test1:
; SOFT: lsr r1, r1, #31
; SOFT: bfi r0, r1, #31, #1
-; HARD: test1:
+; HARD-LABEL: test1:
; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
; HARD: vbsl [[REG1]], d
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
define double @test2(double %x, double %y) nounwind {
entry:
-; SOFT: test2:
+; SOFT-LABEL: test2:
; SOFT: lsr r2, r3, #31
; SOFT: bfi r1, r2, #31, #1
-; HARD: test2:
+; HARD-LABEL: test2:
; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
; HARD: vshl.i64 [[REG2]], [[REG2]], #32
; HARD: vbsl [[REG2]], d1, d0
define double @test3(double %x, double %y, double %z) nounwind {
entry:
-; SOFT: test3:
+; SOFT-LABEL: test3:
; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
; SOFT: vbsl [[REG3]],
; rdar://9287902
define float @test4() nounwind {
entry:
-; SOFT: test4:
+; SOFT-LABEL: test4:
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
ret float %0
}
-; VFP2: test:
+; VFP2-LABEL: test:
; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
-; NFP1: test:
+; NFP1-LABEL: test:
; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
-; NFP0: test:
+; NFP0-LABEL: test:
; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
ret float %0
}
-; VFP2: test:
+; VFP2-LABEL: test:
; VFP2: vmul.f32 s
-; NFP1: test:
+; NFP1-LABEL: test:
; NFP1: vmul.f32 d
-; NFP0: test:
+; NFP0-LABEL: test:
; NFP0: vmul.f32 s
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
; CORTEXA8: vmul.f32 s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
; CORTEXA8U: vmul.f32 d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
; CORTEXA9: vmul.f32 s
; VFP2: test2
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
ret float %retval
}
-; VFP2: test1:
+; VFP2-LABEL: test1:
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
-; NFP1: test1:
+; NFP1-LABEL: test1:
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
-; NFP0: test1:
+; NFP0-LABEL: test1:
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
-; CORTEXA8: test1:
+; CORTEXA8-LABEL: test1:
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
-; CORTEXA8U: test1:
+; CORTEXA8U-LABEL: test1:
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
-; CORTEXA9: test1:
+; CORTEXA9-LABEL: test1:
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
define float @test2(float* %a) {
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
ret float %retval
}
-; VFP2: test2:
+; VFP2-LABEL: test2:
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
-; NFP1: test2:
+; NFP1-LABEL: test2:
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
-; NFP0: test2:
+; NFP0-LABEL: test2:
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
-; CORTEXA8: test2:
+; CORTEXA8-LABEL: test2:
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
-; CORTEXA8U: test2:
+; CORTEXA8U-LABEL: test2:
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
-; CORTEXA9: test2:
+; CORTEXA9-LABEL: test2:
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
define i32 @test1(float %a, float %b) {
-; VFP2: test1:
+; VFP2-LABEL: test1:
; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
-; NEON: test1:
+; NEON-LABEL: test1:
; NEON: vadd.f32 [[D0:d[0-9]+]]
; NEON: vcvt.s32.f32 d0, [[D0]]
entry:
}
define i32 @test2(float %a, float %b) {
-; VFP2: test2:
+; VFP2-LABEL: test2:
; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
-; NEON: test2:
+; NEON-LABEL: test2:
; NEON: vadd.f32 [[D0:d[0-9]+]]
; NEON: vcvt.u32.f32 d0, [[D0]]
entry:
}
define float @test3(i32 %a, i32 %b) {
-; VFP2: test3:
+; VFP2-LABEL: test3:
; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
-; NEON: test3:
+; NEON-LABEL: test3:
; NEON: vcvt.f32.u32 d
entry:
%0 = add i32 %a, %b
}
define float @test4(i32 %a, i32 %b) {
-; VFP2: test4:
+; VFP2-LABEL: test4:
; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
-; NEON: test4:
+; NEON-LABEL: test4:
; NEON: vcvt.f32.s32 d
entry:
%0 = add i32 %a, %b
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: ldr {{.*, \[.*]}}, -r2
; CHECK-NOT: ldr
define i32 @test1(i32 %a, i32 %b, i32 %c) {
ret i32 %tmp5
}
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: ldr {{.*, \[.*\]}}, #-16
; CHECK-NOT: ldr
define i32 @test2(i32 %a, i32 %b) {
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: ldr {{.*!}}
; CHECK-NOT: ldr
define i32* @test1(i32* %X, i32* %dest) {
ret i32* %Y
}
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: ldr {{.*!}}
; CHECK-NOT: ldr
define i32 @test2(i32 %a, i32 %b, i32 %c) {
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vabs.s32 q
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
}
define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: vabs.s32 q
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer
}
define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: vabs.s16 q
%tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer
}
define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: vabs.s8 q
%tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer
}
define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: vabs.s32 q
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sle <4 x i32> %a, zeroinitializer
}
define <2 x i32> @test6(<2 x i32> %a) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: vabs.s32 d
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
}
define <2 x i32> @test7(<2 x i32> %a) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: vabs.s32 d
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sge <2 x i32> %a, zeroinitializer
}
define <4 x i16> @test8(<4 x i16> %a) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: vabs.s16 d
%tmp1neg = sub <4 x i16> zeroinitializer, %a
%b = icmp sgt <4 x i16> %a, zeroinitializer
}
define <8 x i8> @test9(<8 x i8> %a) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: vabs.s8 d
%tmp1neg = sub <8 x i8> zeroinitializer, %a
%b = icmp slt <8 x i8> %a, zeroinitializer
}
define <2 x i32> @test10(<2 x i32> %a) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: vabs.s32 d
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sle <2 x i32> %a, zeroinitializer
ret i32 %tmp57
}
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: pkhtb r0, r0, r1, asr #16
define i32 @test9(i32 %src1, i32 %src2) {
entry:
ret i32 %tmp3
}
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: pkhtb r0, r0, r1, asr #17
define i32 @test10(i32 %src1, i32 %src2) {
entry:
; rdar://9147637
define i32 @test3(i16 zeroext %a) nounwind {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: revsh r0, r0
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
%1 = sext i16 %0 to i32
define i32 @test4(i16 zeroext %a) nounwind {
entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: revsh r0, r0
%conv = zext i16 %a to i32
%shr9 = lshr i16 %a, 8
define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
-; A8: test1:
+; A8-LABEL: test1:
; A8: add r0, r0, r1, lsl r2
-; A9: test1:
+; A9-LABEL: test1:
; A9: add r0, r0, r1, lsl r2
%shift.upgrd.1 = zext i8 %sh to i32
%A = shl i32 %Y, %shift.upgrd.1
}
define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
-; A8: test2:
+; A8-LABEL: test2:
; A8: bic r0, r0, r1, asr r2
-; A9: test2:
+; A9-LABEL: test2:
; A9: bic r0, r0, r1, asr r2
%shift.upgrd.2 = zext i8 %sh to i32
%A = ashr i32 %Y, %shift.upgrd.2
define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
entry:
-; A8: test3:
+; A8-LABEL: test3:
; A8: ldr r0, [r0, r2, lsl #2]
; A8: ldr r1, [r1, r2, lsl #2]
; lsl #2 is free
-; A9: test3:
+; A9-LABEL: test3:
; A9: ldr r0, [r0, r2, lsl #2]
; A9: ldr r1, [r1, r2, lsl #2]
%tmp1 = shl i32 %offset, 2
define fastcc void @test4(i16 %addr) nounwind {
entry:
-; A8: test4:
+; A8-LABEL: test4:
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A8: str [[REG]], [r0, r1, lsl #2]
; A8-NOT: str [[REG]], [r0]
-; A9: test4:
+; A9-LABEL: test4:
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A9: str [[REG]], [r0, r1, lsl #2]
; RUN: llc < %s -march=arm | FileCheck %s
define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: strh {{.*}}[{{.*}}], #-4
%Y = load i32* %X ; <i32> [#uses=1]
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
}
define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: str {{.*}}[{{.*}}],
%Y = load i32* %X ; <i32> [#uses=1]
store i32 %Y, i32* %A
; Release operations only need the store barrier provided by a "dmb ishst",
define void @test_store_release(i32* %p, i32 %v) {
-; CHECK: test_store_release:
+; CHECK-LABEL: test_store_release:
; CHECK: dmb ishst
; CHECK: str
; followed by an acquire does not get reordered. In that case a "dmb ishst" is
; not adequate.
define i32 @test_seq_cst(i32* %p, i32 %v) {
-; CHECK: test_seq_cst:
+; CHECK-LABEL: test_seq_cst:
; CHECK: dmb ishst
; CHECK: str
; CHECK: dmb {{ish$}}
; Also, pure acquire operations should definitely not have an ishst barrier.
define i32 @test_acq(i32* %addr) {
-; CHECK: test_acq:
+; CHECK-LABEL: test_acq:
; CHECK: ldr
; CHECK: dmb {{ish$}}
}
declare noalias i8* @strdup(i8* nocapture) nounwind
-declare i32 @_called_func(i8*, i32*) nounwind
\ No newline at end of file
+declare i32 @_called_func(i8*, i32*) nounwind
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
; Test that we correctly align elements when using va_arg
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: bfc
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
; CHECK: bfc [[REG]], #0, #3
ret i64 %0
}
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK-NOT: bfc
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
; CHECK: bfc [[REG]], #0, #3
}
define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_s64:
+; CHECK-LABEL: test_vbsl_s64:
; CHECK: vbsl d
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
ret <1 x i64> %vbsl3.i
}
define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_u64:
+; CHECK-LABEL: test_vbsl_u64:
; CHECK: vbsl d
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
ret <1 x i64> %vbsl3.i
}
define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_s64:
+; CHECK-LABEL: test_vbslq_s64:
; CHECK: vbsl q
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
ret <2 x i64> %vbsl3.i
}
define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_u64:
+; CHECK-LABEL: test_vbslq_u64:
; CHECK: vbsl q
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
ret <2 x i64> %vbsl3.i
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd:
+;CHECK-LABEL: test_vextd:
;CHECK: vext
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextRd:
+;CHECK-LABEL: test_vextRd:
;CHECK: vext
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextq:
+;CHECK-LABEL: test_vextq:
;CHECK: vext
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq:
+;CHECK-LABEL: test_vextRq:
;CHECK: vext
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: test_vextd16:
+;CHECK-LABEL: test_vextd16:
;CHECK: vext
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: test_vextq32:
+;CHECK-LABEL: test_vextq32:
;CHECK: vext
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
; Undef shuffle indices should not prevent matching to VEXT:
define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd_undef:
+;CHECK-LABEL: test_vextd_undef:
;CHECK: vext
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq_undef:
+;CHECK-LABEL: test_vextRq_undef:
;CHECK: vext
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2:
+;CHECK-LABEL: test_vextq_undef_op2:
;CHECK: vext
entry:
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
}
define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2:
+;CHECK-LABEL: test_vextd_undef_op2:
;CHECK: vext
entry:
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2_undef:
+;CHECK-LABEL: test_vextq_undef_op2_undef:
;CHECK: vext
entry:
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
}
define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2_undef:
+;CHECK-LABEL: test_vextd_undef_op2_undef:
;CHECK: vext
entry:
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
; Also checks interleaving of sources is handled correctly.
; Essence: a vext is used on %A and something saner than stack load/store for final result.
define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_interleaved:
+;CHECK-LABEL: test_interleaved:
;CHECK: vext.16
;CHECK-NOT: vext.16
;CHECK: vzip.16
; An undef in the shuffle list should still be optimizable
define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_undef:
+;CHECK-LABEL: test_undef:
;CHECK: vzip.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
; Try to look for fallback to by-element inserts.
define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
-;CHECK: test_multisource:
+;CHECK-LABEL: test_multisource:
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
;CHECK: vmov.16 [[REG]][1]
;CHECK: vmov.16 [[REG]][2]
; We don't handle shuffles using more than half of a 128-bit vector.
; Again, test for fallback to by-element inserts.
define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
-;CHECK: test_largespan:
+;CHECK-LABEL: test_largespan:
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
;CHECK: vmov.16 [[REG]][1]
;CHECK: vmov.16 [[REG]][2]
; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
; lowering loop can result otherwise).
define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_illegal:
+;CHECK-LABEL: test_illegal:
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
;CHECK: vmov.16 [[REG]][1]
;CHECK: vmov.16 [[REG]][2]
; PR11129
; Make sure this doesn't crash
define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
-; CHECK: test_elem_mismatch:
+; CHECK-LABEL: test_elem_mismatch:
; CHECK: vstr
%tmp0 = load <2 x i64>* %src, align 16
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
declare double @fabs(double)
define void @test_abs(float* %P, double* %D) {
-;CHECK: test_abs:
+;CHECK-LABEL: test_abs:
%a = load float* %P ; <float> [#uses=1]
;CHECK: vabs.f32
%b = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
}
define void @test_add(float* %P, double* %D) {
-;CHECK: test_add:
+;CHECK-LABEL: test_add:
%a = load float* %P ; <float> [#uses=2]
%b = fadd float %a, %a ; <float> [#uses=1]
store float %b, float* %P
}
define void @test_ext_round(float* %P, double* %D) {
-;CHECK: test_ext_round:
+;CHECK-LABEL: test_ext_round:
%a = load float* %P ; <float> [#uses=1]
;CHECK: vcvt.f64.f32
;CHECK: vcvt.f32.f64
}
define void @test_fma(float* %P1, float* %P2, float* %P3) {
-;CHECK: test_fma:
+;CHECK-LABEL: test_fma:
%a1 = load float* %P1 ; <float> [#uses=1]
%a2 = load float* %P2 ; <float> [#uses=1]
%a3 = load float* %P3 ; <float> [#uses=1]
}
define i32 @test_ftoi(float* %P1) {
-;CHECK: test_ftoi:
+;CHECK-LABEL: test_ftoi:
%a1 = load float* %P1 ; <float> [#uses=1]
;CHECK: vcvt.s32.f32
%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
}
define i32 @test_ftou(float* %P1) {
-;CHECK: test_ftou:
+;CHECK-LABEL: test_ftou:
%a1 = load float* %P1 ; <float> [#uses=1]
;CHECK: vcvt.u32.f32
%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
}
define i32 @test_dtoi(double* %P1) {
-;CHECK: test_dtoi:
+;CHECK-LABEL: test_dtoi:
%a1 = load double* %P1 ; <double> [#uses=1]
;CHECK: vcvt.s32.f64
%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
}
define i32 @test_dtou(double* %P1) {
-;CHECK: test_dtou:
+;CHECK-LABEL: test_dtou:
%a1 = load double* %P1 ; <double> [#uses=1]
;CHECK: vcvt.u32.f64
%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
}
define void @test_utod(double* %P1, i32 %X) {
-;CHECK: test_utod:
+;CHECK-LABEL: test_utod:
;CHECK: vcvt.f64.u32
%b1 = uitofp i32 %X to double ; <double> [#uses=1]
store double %b1, double* %P1
}
define void @test_utod2(double* %P1, i8 %X) {
-;CHECK: test_utod2:
+;CHECK-LABEL: test_utod2:
;CHECK: vcvt.f64.u32
%b1 = uitofp i8 %X to double ; <double> [#uses=1]
store double %b1, double* %P1
}
define void @test_cmp(float* %glob, i32 %X) {
-;CHECK: test_cmp:
+;CHECK-LABEL: test_cmp:
entry:
%tmp = load float* %glob ; <float> [#uses=2]
%tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
declare i32 @baz(...)
define void @test_cmpfp0(float* %glob, i32 %X) {
-;CHECK: test_cmpfp0:
+;CHECK-LABEL: test_cmpfp0:
entry:
%tmp = load float* %glob ; <float> [#uses=1]
;CHECK: vcmpe.f32
}
define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
-;CHECK: test_vset_lanef32:
+;CHECK-LABEL: test_vset_lanef32:
;CHECK: vmov.f32 s3, s0
;CHECK: vmov.f64 d0, d1
entry:
define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
entry:
-; CHECK: test_vmul_lanef32:
+; CHECK-LABEL: test_vmul_lanef32:
; CHECK: vmul.f32 d0, d0, d1[0]
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
%1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
entry:
-; CHECK: test_vmul_lanes16:
+; CHECK-LABEL: test_vmul_lanes16:
; CHECK: vmul.i16 d0, d0, d1[1]
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
%1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
entry:
-; CHECK: test_vmul_lanes32:
+; CHECK-LABEL: test_vmul_lanes32:
; CHECK: vmul.i32 d0, d0, d1[1]
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
%1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
entry:
-; CHECK: test_vmulQ_lanef32:
+; CHECK-LABEL: test_vmulQ_lanef32:
; CHECK: vmul.f32 q0, q0, d2[1]
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
%1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
entry:
-; CHECK: test_vmulQ_lanes16:
+; CHECK-LABEL: test_vmulQ_lanes16:
; CHECK: vmul.i16 q0, q0, d2[1]
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
entry:
-; CHECK: test_vmulQ_lanes32:
+; CHECK-LABEL: test_vmulQ_lanes32:
; CHECK: vmul.i32 q0, q0, d2[1]
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
%1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8:
+;CHECK-LABEL: test_vrev64D8:
;CHECK: vrev64.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
}
define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev64D16:
+;CHECK-LABEL: test_vrev64D16:
;CHECK: vrev64.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
}
define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK: test_vrev64D32:
+;CHECK-LABEL: test_vrev64D32:
;CHECK: vrev64.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
}
define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK: test_vrev64Df:
+;CHECK-LABEL: test_vrev64Df:
;CHECK: vrev64.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
}
define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev64Q8:
+;CHECK-LABEL: test_vrev64Q8:
;CHECK: vrev64.8
%tmp1 = load <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
}
define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev64Q16:
+;CHECK-LABEL: test_vrev64Q16:
;CHECK: vrev64.16
%tmp1 = load <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
}
define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK: test_vrev64Q32:
+;CHECK-LABEL: test_vrev64Q32:
;CHECK: vrev64.32
%tmp1 = load <4 x i32>* %A
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
}
define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK: test_vrev64Qf:
+;CHECK-LABEL: test_vrev64Qf:
;CHECK: vrev64.32
%tmp1 = load <4 x float>* %A
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
}
define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev32D8:
+;CHECK-LABEL: test_vrev32D8:
;CHECK: vrev32.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
}
define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev32D16:
+;CHECK-LABEL: test_vrev32D16:
;CHECK: vrev32.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
}
define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev32Q8:
+;CHECK-LABEL: test_vrev32Q8:
;CHECK: vrev32.8
%tmp1 = load <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
}
define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16:
+;CHECK-LABEL: test_vrev32Q16:
;CHECK: vrev32.16
%tmp1 = load <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
}
define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev16D8:
+;CHECK-LABEL: test_vrev16D8:
;CHECK: vrev16.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
}
define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev16Q8:
+;CHECK-LABEL: test_vrev16Q8:
;CHECK: vrev16.8
%tmp1 = load <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
; Undef shuffle indices should not prevent matching to VREV:
define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8_undef:
+;CHECK-LABEL: test_vrev64D8_undef:
;CHECK: vrev64.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
}
define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16_undef:
+;CHECK-LABEL: test_vrev32Q16_undef:
;CHECK: vrev32.16
%tmp1 = load <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
; A vcombine feeding a VREV should not obscure things. Radar 8597007.
define void @test_with_vcombine(<4 x float>* %v) nounwind {
-;CHECK: test_with_vcombine:
+;CHECK-LABEL: test_with_vcombine:
;CHECK-NOT: vext
;CHECK: vrev64.32
%tmp1 = load <4 x float>* %v, align 16
; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
; to <2 x i16> when stored to memory.
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK: test_vrev64:
+; CHECK-LABEL: test_vrev64:
; CHECK: vst1.32
entry:
%0 = bitcast <4 x i16>* %source to <8 x i16>*
%tmp2122 = trunc i128 %tmp21 to i64
store i64 %tmp2122, i64* %RH
ret void
-}
\ No newline at end of file
+}
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
ret i32 0
-}
\ No newline at end of file
+}
call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
ret i32 0
-}
\ No newline at end of file
+}
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
ret i32 0
-}
\ No newline at end of file
+}
ret:
ret i32 -1
-}
\ No newline at end of file
+}
%tmp2122 = trunc i128 %tmp21 to i64
store i64 %tmp2122, i64* %RH
ret void
-}
\ No newline at end of file
+}
%tmp = load i65* @i65_l
store i65 %tmp, i65* @i65_s
ret void
-}
\ No newline at end of file
+}
; Function Attrs: nounwind
define i16 @test(i16 %i) #0 {
entry:
-; CHECK: test:
+; CHECK-LABEL: test:
%retval = alloca i16, align 2
%i.addr = alloca i16, align 2
store i16 %i, i16* %i.addr, align 2
; 16: save $ra, $s0, $s1, 2040
; 16: addiu $sp, -48 # 16 bit inst
; 16: addiu $sp, 48 # 16 bit inst
-; 16: restore $ra, $s0, $s1, 2040
\ No newline at end of file
+; 16: restore $ra, $s0, $s1, 2040
; RUN: llc -march=mipsel < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
-; CHECK: test_blez:
+; CHECK-LABEL: test_blez:
; CHECK: blez ${{[0-9]+}}, $BB
define void @test_blez(i32 %a) {
declare void @foo1()
-; CHECK: test_bgez:
+; CHECK-LABEL: test_bgez:
; CHECK: bgez ${{[0-9]+}}, $BB
define void @test_bgez(i32 %a) {
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
-; R1: test_lbux:
+; R1-LABEL: test_lbux:
; R1: lbux ${{[0-9]+}}
define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
ret i8 %0
}
-; R1: test_lhx:
+; R1-LABEL: test_lhx:
; R1: lhx ${{[0-9]+}}
define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
ret i16 %0
}
-; R1: test_lwx:
+; R1-LABEL: test_lwx:
; R1: lwx ${{[0-9]+}}
define i32 @test_lwx(i32* nocapture %b, i32 %i) {
ret i32 %0
}
-; R1: test_add_v2q15_:
+; R1-LABEL: test_add_v2q15_:
; R1: addq.ph ${{[0-9]+}}
define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: test_sub_v2q15_:
+; R1-LABEL: test_sub_v2q15_:
; R1: subq.ph ${{[0-9]+}}
define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
ret { i32 } %.fca.0.insert
}
-; R2: test_mul_v2q15_:
+; R2-LABEL: test_mul_v2q15_:
; R2: mul.ph ${{[0-9]+}}
; mul.ph is an R2 instruction. Check that multiply node gets expanded.
-; R1: test_mul_v2q15_:
+; R1-LABEL: test_mul_v2q15_:
; R1: mul ${{[0-9]+}}
; R1: mul ${{[0-9]+}}
ret { i32 } %.fca.0.insert
}
-; R1: test_add_v4i8_:
+; R1-LABEL: test_add_v4i8_:
; R1: addu.qb ${{[0-9]+}}
define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: test_sub_v4i8_:
+; R1-LABEL: test_sub_v4i8_:
; R1: subu.qb ${{[0-9]+}}
define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
}
; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
-; R2: test_mul_v4i8_:
+; R2-LABEL: test_mul_v4i8_:
; R2: mul ${{[0-9]+}}
; R2: mul ${{[0-9]+}}
; R2: mul ${{[0-9]+}}
ret { i32 } %.fca.0.insert
}
-; R1: test_addsc:
+; R1-LABEL: test_addsc:
; R1: addsc ${{[0-9]+}}
; R1: addwc ${{[0-9]+}}
; Check that shift node is expanded if splat element size is not 16-bit.
;
-; R1: test_vector_splat_imm_v2q15:
+; R1-LABEL: test_vector_splat_imm_v2q15:
; R1-NOT: shll.ph
define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
; Check that shift node is expanded if splat element size is not 8-bit.
;
-; R1: test_vector_splat_imm_v4i8:
+; R1-LABEL: test_vector_splat_imm_v4i8:
; R1-NOT: shll.qb
define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
;
-; R1: test_shift_amount_v2q15:
+; R1-LABEL: test_shift_amount_v2q15:
; R1-NOT: shll.ph
define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
;
-; R1: test_shift_amount_v4i8:
+; R1-LABEL: test_shift_amount_v4i8:
; R1-NOT: shll.qb
define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; 32: test_float_int_:
+; 32-LABEL: test_float_int_:
; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
ret float %conv
}
-; 32: test_double_int_:
+; 32-LABEL: test_double_int_:
; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
-; 64: test_double_int_:
+; 64-LABEL: test_double_int_:
; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
ret double %conv
}
-; 64: test_float_LL_:
+; 64-LABEL: test_float_LL_:
; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
ret float %conv
}
-; 64: test_double_LL_:
+; 64-LABEL: test_double_LL_:
; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
-; 32: test_sqrtf_float_:
+; 32-LABEL: test_sqrtf_float_:
; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: c.un.s $f[[R0]], $f[[R0]]
-; 64: test_sqrtf_float_:
+; 64-LABEL: test_sqrtf_float_:
; 64: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: c.un.s $f[[R0]], $f[[R0]]
declare float @sqrtf(float)
-; 32: test_sqrt_double_:
+; 32-LABEL: test_sqrt_double_:
; 32: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: c.un.d $f[[R0]], $f[[R0]]
-; 64: test_sqrt_double_:
+; 64-LABEL: test_sqrt_double_:
; 64: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: c.un.d $f[[R0]], $f[[R0]]
; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: cmpi ${{[0-9]+}}, 1000
-; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
\ No newline at end of file
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
declare i16 @llvm.ctpop.i16(i16)
declare i32 @llvm.ctpop.i32(i32)
-declare i64 @llvm.ctpop.i64(i64)
\ No newline at end of file
+declare i64 @llvm.ctpop.i64(i64)
ret void
}
-
\ No newline at end of file
+
!1 = metadata !{ i32 4 }
declare i32 @llvm.nvvm.ldu.global.i.i32(i32*)
-declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
\ No newline at end of file
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
%ret = fdiv float 1.0, %val
ret float %ret
}
-
\ No newline at end of file
+
%add17 = add nsw i16 %shr9, %shr
store i16 %add17, i16* %p2, align 4
ret void
-}
\ No newline at end of file
+}
store i64 %z2, i64* %xx, align 4
ret void
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: sldi {{.*}}, {{.*}}, 32
; Note: it's okay if someday CodeGen gets smart enough to optimize out
; the shift.
%D = fmul double %A, %B ; <double> [#uses=1]
%E = fadd double %D, %C ; <double> [#uses=1]
ret double %E
-; CHECK: test_FMADD1:
+; CHECK-LABEL: test_FMADD1:
; CHECK: fmadd
; CHECK-NEXT: blr
}
%D = fmul double %A, %B ; <double> [#uses=1]
%E = fadd double %D, %C ; <double> [#uses=1]
ret double %E
-; CHECK: test_FMADD2:
+; CHECK-LABEL: test_FMADD2:
; CHECK: fmadd
; CHECK-NEXT: blr
}
%D = fmul double %A, %B ; <double> [#uses=1]
%E = fsub double %D, %C ; <double> [#uses=1]
ret double %E
-; CHECK: test_FMSUB:
+; CHECK-LABEL: test_FMSUB:
; CHECK: fmsub
; CHECK-NEXT: blr
}
%E = fadd double %D, %C ; <double> [#uses=1]
%F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
ret double %F
-; CHECK: test_FNMADD1:
+; CHECK-LABEL: test_FNMADD1:
; CHECK: fnmadd
; CHECK-NEXT: blr
}
%E = fadd double %C, %D ; <double> [#uses=1]
%F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
ret double %F
-; CHECK: test_FNMADD2:
+; CHECK-LABEL: test_FNMADD2:
; CHECK: fnmadd
; CHECK-NEXT: blr
}
%D = fmul double %A, %B ; <double> [#uses=1]
%E = fsub double %C, %D ; <double> [#uses=1]
ret double %E
-; CHECK: test_FNMSUB1:
+; CHECK-LABEL: test_FNMSUB1:
; CHECK: fnmsub
; CHECK-NEXT: blr
}
%E = fsub double %D, %C ; <double> [#uses=1]
%F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
ret double %F
-; CHECK: test_FNMSUB2:
+; CHECK-LABEL: test_FNMSUB2:
; CHECK: fnmsub
; CHECK-NEXT: blr
}
%E = fsub float %D, %C ; <float> [#uses=1]
%F = fsub float -0.000000e+00, %E ; <float> [#uses=1]
ret float %F
-; CHECK: test_FNMSUBS:
+; CHECK-LABEL: test_FNMSUBS:
; CHECK: fnmsubs
; CHECK-NEXT: blr
}
ret i32 %0
}
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
ret i32 %0
}
-; CHECK: test_fn_static:
+; CHECK-LABEL: test_fn_static:
; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
ret i32 %0
}
-; CHECK: test_file_static:
+; CHECK-LABEL: test_file_static:
; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
; CHECK: .quad 4562098671269285104
-; CHECK: test_double_const:
+; CHECK-LABEL: test_double_const:
; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
ret i32 %0
}
-; MEDIUM: test_fn_static:
+; MEDIUM-LABEL: test_fn_static:
; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
; MEDIUM: .local [[VAR]]
; MEDIUM: .comm [[VAR]],4,4
-; LARGE: test_fn_static:
+; LARGE-LABEL: test_fn_static:
; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
ret i32 %0
}
-; MEDIUM: test_file_static:
+; MEDIUM-LABEL: test_file_static:
; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
; MEDIUM: [[VAR]]:
; MEDIUM: .long 5
-; LARGE: test_file_static:
+; LARGE-LABEL: test_file_static:
; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
; MEDIUM: .quad 4562098671269285104
-; MEDIUM: test_double_const:
+; MEDIUM-LABEL: test_double_const:
; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE: .quad 4562098671269285104
-; LARGE: test_double_const:
+; LARGE-LABEL: test_double_const:
; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
ret i32 %5
}
-; CHECK: test_jump_table:
+; CHECK-LABEL: test_jump_table:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
ret i32 %0
}
-; CHECK: test_tentative:
+; CHECK-LABEL: test_tentative:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
declare signext i32 @foo(i32 signext)
-; CHECK: test_fnaddr:
+; CHECK-LABEL: test_fnaddr:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: .section .toc
ret i8 %1
}
-; CHECK: test_avext:
+; CHECK-LABEL: test_avext:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: lbz {{[0-9]+}}, 0([[REG2]])
ret i32 %0
}
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
ret i32 %0
}
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
; %val1 is a load live out of %entry. It should be hoisted
; above the add.
-; CHECK: testload:
+; CHECK-LABEL: testload:
; CHECK: %entry
; CHECK: lwz
; CHECK: addi
; The prefetch gets a default latency of 3 cycles and should be hoisted
; above the add.
;
-; CHECK: testprefetch:
+; CHECK-LABEL: testprefetch:
; CHECK: %entry
; CHECK: dcbt
; CHECK: addi
; Calls to local function does not require the TOC restore 'nop'
define void @test_direct() nounwind readnone {
-; CHECK: test_direct:
+; CHECK-LABEL: test_direct:
tail call void @foo() nounwind
; CHECK: bl foo
; CHECK-NOT: nop
; Calls to weak function requires a TOC restore 'nop' because they
; may be overridden in a different module.
define void @test_weak() nounwind readnone {
-; CHECK: test_weak:
+; CHECK-LABEL: test_weak:
tail call void @foo_weak() nounwind
; CHECK: bl foo
; CHECK-NEXT: nop
; Indirect calls requires a full stub creation
define void @test_indirect(void ()* nocapture %fp) nounwind {
-; CHECK: test_indirect:
+; CHECK-LABEL: test_indirect:
tail call void %fp() nounwind
; CHECK: ld [[FP:[0-9]+]], 0(3)
; CHECK: ld 11, 16(3)
; Absolute vales should be have the TOC restore 'nop'
define void @test_abs() nounwind {
-; CHECK: test_abs:
+; CHECK-LABEL: test_abs:
tail call void inttoptr (i64 1024 to void ()*)() nounwind
; CHECK: bla 1024
; CHECK-NEXT: nop
; External functions call should also have a 'nop'
define double @test_external(double %x) nounwind {
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
%call = tail call double @sin(double %x) nounwind
; CHECK: bl sin
; CHECK-NEXT: nop
%call = tail call float @floorf(float %x) nounwind readnone
ret float %call
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: frim 1, 1
; CHECK-FM: test1:
%call = tail call double @floor(double %x) nounwind readnone
ret double %call
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: frim 1, 1
; CHECK-FM: test2:
%call = tail call float @nearbyintf(float %x) nounwind readnone
ret float %call
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK-NOT: frin
; CHECK-FM: test3:
%call = tail call double @nearbyint(double %x) nounwind readnone
ret double %call
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK-NOT: frin
; CHECK-FM: test4:
%call = tail call float @ceilf(float %x) nounwind readnone
ret float %call
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: frip 1, 1
; CHECK-FM: test5:
%call = tail call double @ceil(double %x) nounwind readnone
ret double %call
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: frip 1, 1
; CHECK-FM: test6:
%call = tail call float @truncf(float %x) nounwind readnone
ret float %call
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: friz 1, 1
; CHECK-FM: test9:
%call = tail call double @trunc(double %x) nounwind readnone
ret double %call
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: friz 1, 1
; CHECK-FM: test10:
store float %call, float* %y
ret void
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK-NOT: frin
; CHECK-FM: test11:
store double %call, double* %y
ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK-NOT: frin
; CHECK-FM: test12:
ret void
}
-; CHECK: test_v4i32_pos_even:
+; CHECK-LABEL: test_v4i32_pos_even:
; CHECK: vspltisw [[REG1:[0-9]+]], 9
; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v4i32_neg_even:
+; CHECK-LABEL: test_v4i32_neg_even:
; CHECK: vspltisw [[REG1:[0-9]+]], -14
; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v8i16_pos_even:
+; CHECK-LABEL: test_v8i16_pos_even:
; CHECK: vspltish [[REG1:[0-9]+]], 15
; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v8i16_neg_even:
+; CHECK-LABEL: test_v8i16_neg_even:
; CHECK: vspltish [[REG1:[0-9]+]], -16
; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v16i8_pos_even:
+; CHECK-LABEL: test_v16i8_pos_even:
; CHECK: vspltisb [[REG1:[0-9]+]], 8
; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v16i8_neg_even:
+; CHECK-LABEL: test_v16i8_neg_even:
; CHECK: vspltisb [[REG1:[0-9]+]], -9
; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
ret void
}
-; CHECK: test_v4i32_pos_odd:
+; CHECK-LABEL: test_v4i32_pos_odd:
; CHECK: vspltisw [[REG2:[0-9]+]], -16
; CHECK: vspltisw [[REG1:[0-9]+]], 11
; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
ret void
}
-; CHECK: test_v4i32_neg_odd:
+; CHECK-LABEL: test_v4i32_neg_odd:
; CHECK: vspltisw [[REG2:[0-9]+]], -16
; CHECK: vspltisw [[REG1:[0-9]+]], -11
; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
ret void
}
-; CHECK: test_v8i16_pos_odd:
+; CHECK-LABEL: test_v8i16_pos_odd:
; CHECK: vspltish [[REG2:[0-9]+]], -16
; CHECK: vspltish [[REG1:[0-9]+]], 15
; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
ret void
}
-; CHECK: test_v8i16_neg_odd:
+; CHECK-LABEL: test_v8i16_neg_odd:
; CHECK: vspltish [[REG2:[0-9]+]], -16
; CHECK: vspltish [[REG1:[0-9]+]], -15
; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
ret void
}
-; CHECK: test_v16i8_pos_odd:
+; CHECK-LABEL: test_v16i8_pos_odd:
; CHECK: vspltisb [[REG2:[0-9]+]], -16
; CHECK: vspltisb [[REG1:[0-9]+]], 1
; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
ret void
}
-; CHECK: test_v16i8_neg_odd:
+; CHECK-LABEL: test_v16i8_neg_odd:
; CHECK: vspltisb [[REG2:[0-9]+]], -16
; CHECK: vspltisb [[REG1:[0-9]+]], -1
; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]
ret i8* %A
}
-; P32: test1:
+; P32-LABEL: test1:
; P32: lwz r2, 0(r3)
; P32: addi r4, r2, 4
; P32: stw r4, 0(r3)
; P32: lwz r3, 0(r2)
; P32: blr
-; P64: test1:
+; P64-LABEL: test1:
; P64: ld r2, 0(r3)
; P64: addi r4, r2, 8
; P64: std r4, 0(r3)
store <4 x float> %tmp13, <4 x float>* %P3
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: CPI
}
define <4 x i32> @test_30() nounwind {
ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
; CHECK: vspltisw
; CHECK-NEXT: vadduwm
; CHECK-NEXT: blr
define <4 x i32> @test_29() nounwind {
ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
; CHECK: vspltisw
; CHECK-NEXT: vspltisw
; CHECK-NEXT: vsubuwm
define <8 x i16> @test_n30() nounwind {
ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
; CHECK: vspltish
; CHECK-NEXT: vadduhm
; CHECK-NEXT: blr
define <16 x i8> @test_n104() nounwind {
ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
; CHECK: vspltisb
; CHECK-NEXT: vslb
; CHECK-NEXT: blr
define <4 x i32> @test_vsldoi() nounwind {
ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
; CHECK: vspltisw
; CHECK-NEXT: vsldoi
; CHECK-NEXT: blr
define <8 x i16> @test_vsldoi_65023() nounwind {
ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
; CHECK: vspltish
; CHECK-NEXT: vsldoi
; CHECK-NEXT: blr
define <4 x i32> @test_rol() nounwind {
ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
; CHECK: vspltisw
; CHECK-NEXT: vrlw
; CHECK-NEXT: blr
%tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp3
}
-; CHECK: test_v4i32:
+; CHECK-LABEL: test_v4i32:
; CHECK: vmsumuhm
; CHECK-NOT: mullw
%tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
ret <8 x i16> %tmp3
}
-; CHECK: test_v8i16:
+; CHECK-LABEL: test_v8i16:
; CHECK: vmladduhm
; CHECK-NOT: mullw
%tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
ret <16 x i8> %tmp3
}
-; CHECK: test_v16i8:
+; CHECK-LABEL: test_v16i8:
; CHECK: vmuloub
; CHECK: vmuleub
; CHECK-NOT: mullw
; Check the creation of a negative zero float vector by creating a vector of
; all bits set and shifting it 31 bits to left, resulting a an vector of
; 4 x 0x80000000 (-0.0 as float).
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
; CHECK: vmaddfp
define i32 @test0(i32 %X) {
%tmp.1 = add i32 %X, 1
ret i32 %tmp.1
-; CHECK: test0:
+; CHECK-LABEL: test0:
; CHECK: add %o0, 1, %o0
}
%A = xor i32 %X, %Y
%B = xor i32 %A, -1
ret i32 %B
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: xnor %o0, %o1, %o0
}
%A = xor i32 %X, -1
%B = xor i32 %A, %Y
ret i32 %B
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: xnor %o0, %o1, %o0
}
; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
-; V8: test_neg:
+; V8-LABEL: test_neg:
; V8: call get_double
; V8: fnegs %f0, %f0
; V8-UNOPT: fmovs {{.+}}, %f0
; V8-UNOPT: fmovs {{.+}}, %f1
-; V9: test_neg:
+; V9-LABEL: test_neg:
; V9: fnegd %f0, %f0
define double @test_neg() {
ret double %1
}
-; V8: test_abs:
+; V8-LABEL: test_abs:
; V8: fabss %f0, %f0
; V8-UNOPT: test_abs:
; V8-UNOPT: fmovs {{.+}}, %f0
; V8-UNOPT: fmovs {{.+}}, %f1
-; V9: test_abs:
+; V9-LABEL: test_abs:
; V9: fabsd %f0, %f0
define double @test_abs() {
define i32 @test1(i32 %X) {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: lsrs r0, r0, #31
icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
zext i1 %0 to i32 ; <i32>:1 [#uses=1]
; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s
define void @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: sub sp, #256
; CHECK: add sp, #256
%tmp = alloca [ 64 x i32 ] , align 4
}
define void @test2() {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: ldr.n r0, LCPI
; CHECK: add sp, r0
; CHECK: subs r4, r7, #4
}
define i32 @test3() {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: ldr.n r1, LCPI
; CHECK: add sp, r1
; CHECK: ldr.n r1, LCPI
; rdar://9147637
define i32 @test3(i16 zeroext %a) nounwind {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: revsh r0, r0
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
%1 = sext i16 %0 to i32
define i32 @test4(i16 zeroext %a) nounwind {
entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: revsh r0, r0
%conv = zext i16 %a to i32
%shr9 = lshr i16 %a, 8
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
define i32 @test(i32 %n) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: mov
; CHECK: return
entry:
}
define i32 @test_dead_cycle(i32 %n) nounwind {
-; CHECK: test_dead_cycle:
+; CHECK-LABEL: test_dead_cycle:
; CHECK: blx
; CHECK-NOT: mov
; CHECK: blx
; Testing that these don't crash/assert. The loop vectorizer can end up
; with odd constructs like this. The code actually generated is incidental.
define <1 x i64> @test_zext(i32 %a) nounwind {
-; CHECK: test_zext:
+; CHECK-LABEL: test_zext:
%Cmp = icmp uge i32 %a, 42
%vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
%Se = zext <1 x i1> %vec to <1 x i64>
}
define <1 x i64> @test_sext(i32 %a) nounwind {
-; CHECK: test_sext:
+; CHECK-LABEL: test_sext:
%Cmp = icmp uge i32 %a, 42
%vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
%Se = sext <1 x i1> %vec to <1 x i64>
; RUN: llc < %s -march=thumb -mattr=+thumb2 -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
define void @test1() {
-; DARWIN: test1:
+; DARWIN-LABEL: test1:
; DARWIN: sub sp, #256
-; LINUX: test1:
+; LINUX-LABEL: test1:
; LINUX: sub sp, #256
%tmp = alloca [ 64 x i32 ] , align 4
ret void
}
define void @test2() {
-; DARWIN: test2:
+; DARWIN-LABEL: test2:
; DARWIN: sub.w sp, sp, #4160
; DARWIN: sub sp, #8
-; LINUX: test2:
+; LINUX-LABEL: test2:
; LINUX: sub.w sp, sp, #4160
; LINUX: sub sp, #8
%tmp = alloca [ 4168 x i8 ] , align 4
}
define i32 @test3() {
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
; DARWIN: push {r4, r7, lr}
; DARWIN: sub.w sp, sp, #805306368
; DARWIN: sub sp, #20
-; LINUX: test3:
+; LINUX-LABEL: test3:
; LINUX: push.w {r4, r7, r11, lr}
; LINUX: sub.w sp, sp, #805306368
; LINUX: sub sp, #16
ret i32 %tmp57
}
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: pkhtb r0, r0, r1, asr #16
define i32 @test9(i32 %src1, i32 %src2) {
entry:
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: strh {{.*}}[{{.*}}], #-4
%Y = load i32* %X ; <i32> [#uses=1]
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
}
define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: str {{.*}}[{{.*}}],
%Y = load i32* %X ; <i32> [#uses=1]
store i32 %Y, i32* %A
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
define i32 @test1(i16 zeroext %z) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: sxth
%r = sext i16 %z to i32
ret i32 %r
}
define i32 @test2(i8 zeroext %z) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: sxtb
%r = sext i8 %z to i32
ret i32 %r
}
define i32 @test3(i16 signext %z) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: uxth
%r = zext i16 %z to i32
ret i32 %r
}
define i32 @test4(i8 signext %z) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: uxtb
%r = zext i8 %z to i32
ret i32 %r
;; This example can't fold the or into an LEA.
define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: orl $1, %{{.*}}
; CHECK: ret
;; This can!
define i32 @test2(i32 %a, i32 %b) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK-NOT: ret
; CHECK: leal 3(,%{{.*}},8)
; CHECK: ret
; RUN: llc < %s -march=x86 | FileCheck %s
define i32 @test(i1 %X) {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: movl $1, %eax
; CHECK: ret
target triple = "i686-apple-darwin9"
define void @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: psrlw $8, %xmm0
; CHECK: ret
target triple = "i386-apple-darwin8"
define void @test() nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: 1 $2 3
; CHECK: ret
; the chains correctly.
; PR10747
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: pextrd $2, %xmm
define <4 x i32> @test(<4 x i32>* %p) {
%v = load <4 x i32>* %p
define i32 @test1(i32 %x) nounwind readnone ssp {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: leal 3(%rdi), %eax
%0 = shl i32 %x, 5 ; <i32> [#uses=1]
%1 = or i32 %0, 3 ; <i32> [#uses=1]
}
define i64 @test2(i8 %A, i8 %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: shrq $4
; CHECK-NOT: movq
; CHECK-NOT: orq
define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
entry:
; No reason to emit an add here, should be an or.
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: orl $3, %edi
%0 = shl i32 %x, 5
%1 = or i32 %0, 3
%and2 = and i32 %b, 16
%or = or i32 %and2, %and
ret i32 %or
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: leal (%rsi,%rdi), %eax
}
%or = or i32 %and2, %and
store i32 %or, i32* %P, align 4
ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: orl
}
define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: cmpl %ecx, %eax
; CHECK-NOT: addl
; CHECK: adcl $0, %eax
}
; Instcombine transforms test1 into test2:
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl
; CHECK-NEXT: addl
; CHECK-NEXT: adcl $0
%dec = sext i1 %cmp to i32
%dec.res = add nsw i32 %dec, %res
ret i32 %dec.res
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpl
; CHECK: sbbl
; CHECK: ret
overflow:
ret i1 false
-; X32: test4:
+; X32-LABEL: test4:
; X32: addl
; X32-NEXT: jo
-; X64: test4:
+; X64-LABEL: test4:
; X64: addl %e[[A1:si|dx]], %e[[A0:di|cx]]
; X64-NEXT: jo
}
carry:
ret i1 false
-; X32: test5:
+; X32-LABEL: test5:
; X32: addl
; X32-NEXT: jb
-; X64: test5:
+; X64-LABEL: test5:
; X64: addl %e[[A1]], %e[[A0]]
; X64-NEXT: jb
}
%tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1]
ret i64 %tmp5
-; X32: test6:
+; X32-LABEL: test6:
; X32: movl 12(%esp), %edx
; X32-NEXT: addl 8(%esp), %edx
; X32-NEXT: movl 4(%esp), %eax
; X32-NEXT: ret
-; X64: test6:
+; X64-LABEL: test6:
; X64: shlq $32, %r[[A1]]
; X64: leaq (%r[[A1]],%r[[A0]]), %rax
; X64: ret
ret {i32, i1} %t
}
-; X64: test7:
+; X64-LABEL: test7:
; X64: addl %e[[A1]], %e
; X64-NEXT: setb %dl
; X64: ret
ret {i64, i1} %final1
}
-; X64: test8:
+; X64-LABEL: test8:
; X64: addq
; X64-NEXT: setb
; X64: ret
%sub = sext i1 %cmp to i32
%cond = add i32 %sub, %y
ret i32 %cond
-; X64: test9:
+; X64-LABEL: test9:
; X64: cmpl $10
; X64: sete
; X64: subl
%obit = extractvalue {i32, i1} %t, 1
ret i1 %obit
-; X32: test10:
+; X32-LABEL: test10:
; X32: incl
; X32-NEXT: seto
-; X64: test10:
+; X64-LABEL: test10:
; X64: incl
; X64-NEXT: seto
}
define i32 @test1() nounwind {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movw %gs:6, %ax
%asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 6) nounwind ; <i16> [#uses=1]
%0 = zext i16 %asmtmp.i to i32 ; <i32> [#uses=1]
define zeroext i16 @test2(i32 %address) nounwind {
entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movw %gs:(%eax), %ax
%asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %address) nounwind ; <i16> [#uses=1]
ret i16 %asmtmp
define void @test3() nounwind {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movl _n, %eax
call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @n) nounwind
ret void
define void @test4() nounwind {
entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movl L_y$non_lazy_ptr, %ecx
; CHECK: movl (%ecx), %eax
call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @y) nounwind
declare void @many_params(i32, i32, i32, i32, i32, i32)
define void @test1() nounwind {
-; ATOM: test1:
+; ATOM-LABEL: test1:
; ATOM: leal -1052(%esp), %esp
; ATOM-NOT: sub
; ATOM: call
; ATOM: leal 1052(%esp), %esp
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: subl
; CHECK: call
; CHECK-NOT: lea
}
define void @test2() nounwind {
-; ATOM: test2:
+; ATOM-LABEL: test2:
; ATOM: leal -28(%esp), %esp
; ATOM: call
; ATOM: leal 28(%esp), %esp
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK-NOT: lea
call void @many_params(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
ret void
}
define void @test3() nounwind {
-; ATOM: test3:
+; ATOM-LABEL: test3:
; ATOM: leal -8(%esp), %esp
; ATOM: leal 8(%esp), %esp
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK-NOT: lea
%x = alloca i32, align 4
%y = alloca i32, align 4
define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: vptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: vptest
; CHECK-NEXT: jae
; CHECK: ret
define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: vptest
; CHECK-NEXT: jae
; CHECK: ret
define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: vptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: vptest
; CHECK-NEXT: je
; CHECK: ret
;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vcvttpd2dqy
; CHECK: ret
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: vcvttpd2dqy
; CHECK: ret
define <4 x float> @test1(<4 x float> %a) nounwind {
%b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
ret <4 x float> %b
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vshufps
; CHECK: vpshufd
}
; rdar://10538417
define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: vinsertf128
%1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
%2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
ret <4 x i64> %c
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: vperm2f128
; CHECK: ret
}
define <8 x float> @test4(float %a) nounwind {
%b = insertelement <8 x float> zeroinitializer, float %a, i32 0
ret <8 x float> %b
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: vinsertf128
}
@x = common global <8 x float> zeroinitializer, align 32
declare i32 @f(i32, ...)
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vmovaps %ymm0, (%rsp)
define void @test1() nounwind uwtable ssp {
entry:
define <8 x i32> @mul_const9(<8 x i32> %x) {
%y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %y
-}
\ No newline at end of file
+}
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
define <8 x i32> @test1(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
ret <8 x i32> %C
}
define <8 x i32> @test2(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 undef, i32 12>
ret <8 x i32> %C
}
define <8 x i32> @test3(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
ret <8 x i32> %C
}
;
define <8 x i32> @test4(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: vpalignr $8
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 10, i32 11, i32 undef, i32 1, i32 14, i32 15, i32 4, i32 5>
ret <8 x i32> %C
}
define <16 x i16> @test5(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 undef, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
ret <16 x i16> %C
}
define <16 x i16> @test6(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
ret <16 x i16> %C
}
define <16 x i16> @test7(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i16> %C
}
define <32 x i8> @test8(<32 x i8> %A, <32 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: palignr $5
%C = shufflevector <32 x i8> %A, <32 x i8> %B, <32 x i32> <i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52>
ret <32 x i8> %C
ret <16 x i16> %shl
}
-; CHECK: test_sllw_1:
+; CHECK-LABEL: test_sllw_1:
; CHECK: vpsllw $0, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_sllw_2:
+; CHECK-LABEL: test_sllw_2:
; CHECK: vpaddw %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_sllw_3:
+; CHECK-LABEL: test_sllw_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_slld_1:
+; CHECK-LABEL: test_slld_1:
; CHECK: vpslld $0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_slld_2:
+; CHECK-LABEL: test_slld_2:
; CHECK: vpaddd %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_slld_3:
+; CHECK-LABEL: test_slld_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_sllq_1:
+; CHECK-LABEL: test_sllq_1:
; CHECK: vpsllq $0, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_sllq_2:
+; CHECK-LABEL: test_sllq_2:
; CHECK: vpaddq %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_sllq_3:
+; CHECK-LABEL: test_sllq_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_sraw_1:
+; CHECK-LABEL: test_sraw_1:
; CHECK: vpsraw $0, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_sraw_2:
+; CHECK-LABEL: test_sraw_2:
; CHECK: vpsraw $1, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_sraw_3:
+; CHECK-LABEL: test_sraw_3:
; CHECK: vpsraw $16, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srad_1:
+; CHECK-LABEL: test_srad_1:
; CHECK: vpsrad $0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srad_2:
+; CHECK-LABEL: test_srad_2:
; CHECK: vpsrad $1, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srad_3:
+; CHECK-LABEL: test_srad_3:
; CHECK: vpsrad $32, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_srlw_1:
+; CHECK-LABEL: test_srlw_1:
; CHECK: vpsrlw $0, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_srlw_2:
+; CHECK-LABEL: test_srlw_2:
; CHECK: vpsrlw $1, %ymm0, %ymm0
; CHECK: ret
ret <16 x i16> %shl
}
-; CHECK: test_srlw_3:
+; CHECK-LABEL: test_srlw_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srld_1:
+; CHECK-LABEL: test_srld_1:
; CHECK: vpsrld $0, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srld_2:
+; CHECK-LABEL: test_srld_2:
; CHECK: vpsrld $1, %ymm0, %ymm0
; CHECK: ret
ret <8 x i32> %shl
}
-; CHECK: test_srld_3:
+; CHECK-LABEL: test_srld_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_srlq_1:
+; CHECK-LABEL: test_srlq_1:
; CHECK: vpsrlq $0, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_srlq_2:
+; CHECK-LABEL: test_srlq_2:
; CHECK: vpsrlq $1, %ymm0, %ymm0
; CHECK: ret
ret <4 x i64> %shl
}
-; CHECK: test_srlq_3:
+; CHECK-LABEL: test_srlq_3:
; CHECK: vxorps %ymm0, %ymm0, %ymm0
; CHECK: ret
define i32 @test_ifchains(i32 %i, i32* %a, i32 %b) {
; Test a chain of ifs, where the block guarded by the if is error handling code
; that is not expected to run.
-; CHECK: test_ifchains:
+; CHECK-LABEL: test_ifchains:
; CHECK: %entry
; CHECK-NOT: .align
; CHECK: %else1
define i32 @test_loop_cold_blocks(i32 %i, i32* %a) {
; Check that we sink cold loop blocks after the hot loop body.
-; CHECK: test_loop_cold_blocks:
+; CHECK-LABEL: test_loop_cold_blocks:
; CHECK: %entry
; CHECK-NOT: .align
; CHECK: %unlikely1
define i32 @test_loop_early_exits(i32 %i, i32* %a) {
; Check that we sink early exit blocks out of loop bodies.
-; CHECK: test_loop_early_exits:
+; CHECK-LABEL: test_loop_early_exits:
; CHECK: %entry
; CHECK: %body1
; CHECK: %body2
define i32 @test_loop_rotate(i32 %i, i32* %a) {
; Check that we rotate conditional exits from the loop to the bottom of the
; loop, eliminating unconditional branches to the top.
-; CHECK: test_loop_rotate:
+; CHECK-LABEL: test_loop_rotate:
; CHECK: %entry
; CHECK: %body1
; CHECK: %body0
define i32 @test_no_loop_rotate(i32 %i, i32* %a) {
; Check that we don't try to rotate a loop which is already laid out with
; fallthrough opportunities into the top and out of the bottom.
-; CHECK: test_no_loop_rotate:
+; CHECK-LABEL: test_no_loop_rotate:
; CHECK: %entry
; CHECK: %body0
; CHECK: %body1
define i32 @test_loop_align(i32 %i, i32* %a) {
; Check that we provide basic loop body alignment with the block placement
; pass.
-; CHECK: test_loop_align:
+; CHECK-LABEL: test_loop_align:
; CHECK: %entry
; CHECK: .align [[ALIGN:[0-9]+]],
; CHECK-NEXT: %body
define i32 @test_nested_loop_align(i32 %i, i32* %a, i32* %b) {
; Check that we provide nested loop body alignment.
-; CHECK: test_nested_loop_align:
+; CHECK-LABEL: test_nested_loop_align:
; CHECK: %entry
; CHECK: .align [[ALIGN]],
; CHECK-NEXT: %loop.body.1
; Test that edges to blocks post-dominated by cold calls are
; marked as not expected to be taken. They should be laid out
; at the bottom.
-; CHECK: test_cold_calls:
+; CHECK-LABEL: test_cold_calls:
; CHECK: %entry
; CHECK: %else
; CHECK: %exit
define i32 @test1(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: xorb
; CHECK-NOT: andb
; CHECK-NOT: shrb
return: ; preds = %entry
ret i32 192
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl 4(%esp), %eax
; CHECK-NEXT: orl 8(%esp), %eax
; CHECK-NEXT: jne LBB1_2
return: ; preds = %entry
ret i32 192
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movl 4(%esp), %eax
; CHECK-NEXT: orl 8(%esp), %eax
; CHECK-NEXT: je LBB2_2
define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: ptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: ptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: ptest
; CHECK-NEXT: jae
; CHECK: ret
define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: ptest
; CHECK-NEXT: jae
; CHECK: ret
define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: ptest
; CHECK-NEXT: jne
; CHECK: ret
define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: ptest
; CHECK-NEXT: je
; CHECK: ret
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.end, label %if.then
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: btq $32
if.then:
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.end, label %if.then
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: testl $-2147483648
if.then:
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test1:
+; SSE-LABEL: test1:
; SSE: movsd
-; NOSSE2: test1:
+; NOSSE2-LABEL: test1:
; NOSSE2: fcmovnbe
-; NOSSE1: test1:
+; NOSSE1-LABEL: test1:
; NOSSE1: fcmovnbe
-; NOCMOV: test1:
+; NOCMOV-LABEL: test1:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test2:
+; SSE-LABEL: test2:
; SSE: movsd
-; NOSSE2: test2:
+; NOSSE2-LABEL: test2:
; NOSSE2: fcmovnb
-; NOSSE1: test2:
+; NOSSE1-LABEL: test2:
; NOSSE1: fcmovnb
-; NOCMOV: test2:
+; NOCMOV-LABEL: test2:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test3:
+; SSE-LABEL: test3:
; SSE: movsd
-; NOSSE2: test3:
+; NOSSE2-LABEL: test3:
; NOSSE2: fcmovb
-; NOSSE1: test3:
+; NOSSE1-LABEL: test3:
; NOSSE1: fcmovb
-; NOCMOV: test3:
+; NOCMOV-LABEL: test3:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test4:
+; SSE-LABEL: test4:
; SSE: movsd
-; NOSSE2: test4:
+; NOSSE2-LABEL: test4:
; NOSSE2: fcmovbe
-; NOSSE1: test4:
+; NOSSE1-LABEL: test4:
; NOSSE1: fcmovbe
-; NOCMOV: test4:
+; NOCMOV-LABEL: test4:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test5:
+; SSE-LABEL: test5:
; SSE: movsd
-; NOSSE2: test5:
+; NOSSE2-LABEL: test5:
; NOSSE2: fstp
-; NOSSE1: test5:
+; NOSSE1-LABEL: test5:
; NOSSE1: fstp
-; NOCMOV: test5:
+; NOCMOV-LABEL: test5:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test6:
+; SSE-LABEL: test6:
; SSE: movsd
-; NOSSE2: test6:
+; NOSSE2-LABEL: test6:
; NOSSE2: fstp
-; NOSSE1: test6:
+; NOSSE1-LABEL: test6:
; NOSSE1: fstp
-; NOCMOV: test6:
+; NOCMOV-LABEL: test6:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test7:
+; SSE-LABEL: test7:
; SSE: movsd
-; NOSSE2: test7:
+; NOSSE2-LABEL: test7:
; NOSSE2: fstp
-; NOSSE1: test7:
+; NOSSE1-LABEL: test7:
; NOSSE1: fstp
-; NOCMOV: test7:
+; NOCMOV-LABEL: test7:
; NOCMOV: fstp
}
%sel = select i1 %cmp, double 99.0, double %x
ret double %sel
-; SSE: test8:
+; SSE-LABEL: test8:
; SSE: movsd
-; NOSSE2: test8:
+; NOSSE2-LABEL: test8:
; NOSSE2: fstp
-; NOSSE1: test8:
+; NOSSE1-LABEL: test8:
; NOSSE1: fstp
-; NOCMOV: test8:
+; NOCMOV-LABEL: test8:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test9:
+; SSE-LABEL: test9:
; SSE: movss
-; NOSSE2: test9:
+; NOSSE2-LABEL: test9:
; NOSSE2: movss
-; NOSSE1: test9:
+; NOSSE1-LABEL: test9:
; NOSSE1: fcmovnbe
-; NOCMOV: test9:
+; NOCMOV-LABEL: test9:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test10:
+; SSE-LABEL: test10:
; SSE: movss
-; NOSSE2: test10:
+; NOSSE2-LABEL: test10:
; NOSSE2: movss
-; NOSSE1: test10:
+; NOSSE1-LABEL: test10:
; NOSSE1: fcmovnb
-; NOCMOV: test10:
+; NOCMOV-LABEL: test10:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test11:
+; SSE-LABEL: test11:
; SSE: movss
-; NOSSE2: test11:
+; NOSSE2-LABEL: test11:
; NOSSE2: movss
-; NOSSE1: test11:
+; NOSSE1-LABEL: test11:
; NOSSE1: fcmovb
-; NOCMOV: test11:
+; NOCMOV-LABEL: test11:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test12:
+; SSE-LABEL: test12:
; SSE: movss
-; NOSSE2: test12:
+; NOSSE2-LABEL: test12:
; NOSSE2: movss
-; NOSSE1: test12:
+; NOSSE1-LABEL: test12:
; NOSSE1: fcmovbe
-; NOCMOV: test12:
+; NOCMOV-LABEL: test12:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test13:
+; SSE-LABEL: test13:
; SSE: movss
-; NOSSE2: test13:
+; NOSSE2-LABEL: test13:
; NOSSE2: movss
-; NOSSE1: test13:
+; NOSSE1-LABEL: test13:
; NOSSE1: fstp
-; NOCMOV: test13:
+; NOCMOV-LABEL: test13:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test14:
+; SSE-LABEL: test14:
; SSE: movss
-; NOSSE2: test14:
+; NOSSE2-LABEL: test14:
; NOSSE2: movss
-; NOSSE1: test14:
+; NOSSE1-LABEL: test14:
; NOSSE1: fstp
-; NOCMOV: test14:
+; NOCMOV-LABEL: test14:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test15:
+; SSE-LABEL: test15:
; SSE: movss
-; NOSSE2: test15:
+; NOSSE2-LABEL: test15:
; NOSSE2: movss
-; NOSSE1: test15:
+; NOSSE1-LABEL: test15:
; NOSSE1: fstp
-; NOCMOV: test15:
+; NOCMOV-LABEL: test15:
; NOCMOV: fstp
}
%sel = select i1 %cmp, float 99.0, float %x
ret float %sel
-; SSE: test16:
+; SSE-LABEL: test16:
; SSE: movss
-; NOSSE2: test16:
+; NOSSE2-LABEL: test16:
; NOSSE2: movss
-; NOSSE1: test16:
+; NOSSE1-LABEL: test16:
; NOSSE1: fstp
-; NOCMOV: test16:
+; NOCMOV-LABEL: test16:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test17:
+; SSE-LABEL: test17:
; SSE: fcmovnbe
-; NOSSE2: test17:
+; NOSSE2-LABEL: test17:
; NOSSE2: fcmovnbe
-; NOSSE1: test17:
+; NOSSE1-LABEL: test17:
; NOSSE1: fcmovnbe
-; NOCMOV: test17:
+; NOCMOV-LABEL: test17:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test18:
+; SSE-LABEL: test18:
; SSE: fcmovnb
-; NOSSE2: test18:
+; NOSSE2-LABEL: test18:
; NOSSE2: fcmovnb
-; NOSSE1: test18:
+; NOSSE1-LABEL: test18:
; NOSSE1: fcmovnb
-; NOCMOV: test18:
+; NOCMOV-LABEL: test18:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test19:
+; SSE-LABEL: test19:
; SSE: fcmovb
-; NOSSE2: test19:
+; NOSSE2-LABEL: test19:
; NOSSE2: fcmovb
-; NOSSE1: test19:
+; NOSSE1-LABEL: test19:
; NOSSE1: fcmovb
-; NOCMOV: test19:
+; NOCMOV-LABEL: test19:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test20:
+; SSE-LABEL: test20:
; SSE: fcmovbe
-; NOSSE2: test20:
+; NOSSE2-LABEL: test20:
; NOSSE2: fcmovbe
-; NOSSE1: test20:
+; NOSSE1-LABEL: test20:
; NOSSE1: fcmovbe
-; NOCMOV: test20:
+; NOCMOV-LABEL: test20:
; NOCMOV: fstp
}
ret x86_fp80 %sel
; We don't emit a branch for fp80, why?
-; SSE: test21:
+; SSE-LABEL: test21:
; SSE: testb
; SSE: fcmovne
-; NOSSE2: test21:
+; NOSSE2-LABEL: test21:
; NOSSE2: testb
; NOSSE2: fcmovne
-; NOSSE1: test21:
+; NOSSE1-LABEL: test21:
; NOSSE1: testb
; NOSSE1: fcmovne
-; NOCMOV: test21:
+; NOCMOV-LABEL: test21:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test22:
+; SSE-LABEL: test22:
; SSE: testb
; SSE: fcmovne
-; NOSSE2: test22:
+; NOSSE2-LABEL: test22:
; NOSSE2: testb
; NOSSE2: fcmovne
-; NOSSE1: test22:
+; NOSSE1-LABEL: test22:
; NOSSE1: testb
; NOSSE1: fcmovne
-; NOCMOV: test22:
+; NOCMOV-LABEL: test22:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test23:
+; SSE-LABEL: test23:
; SSE: testb
; SSE: fcmovne
-; NOSSE2: test23:
+; NOSSE2-LABEL: test23:
; NOSSE2: testb
; NOSSE2: fcmovne
-; NOSSE1: test23:
+; NOSSE1-LABEL: test23:
; NOSSE1: testb
; NOSSE1: fcmovne
-; NOCMOV: test23:
+; NOCMOV-LABEL: test23:
; NOCMOV: fstp
}
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel
-; SSE: test24:
+; SSE-LABEL: test24:
; SSE: testb
; SSE: fcmovne
-; NOSSE2: test24:
+; NOSSE2-LABEL: test24:
; NOSSE2: testb
; NOSSE2: fcmovne
-; NOSSE1: test24:
+; NOSSE1-LABEL: test24:
; NOSSE1: testb
; NOSSE1: fcmovne
-; NOCMOV: test24:
+; NOCMOV-LABEL: test24:
; NOCMOV: fstp
}
%cmp = fcmp olt double %load, %a
%cond = select i1 %cmp, i32 %x, i32 %y
ret i32 %cond
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: ucomisd
; CHECK-NOT: cmov
; CHECK: j
%cmp = fcmp ogt double %a, %b
%cond = select i1 %cmp, i32 %x, i32 %y
ret i32 %cond
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: ucomisd
; CHECK: cmov
}
%cmp = icmp ult i32 %load, %a
%cond = select i1 %cmp, i32 %a, i32 %x
ret i32 %cond
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpl
; CHECK-NOT: cmov
; CHECK: j
%cond = select i1 %cmp, i32 %x, i32 %y
%add = add i32 %cond, %load
ret i32 %add
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: cmpl
; CHECK: cmov
}
%cond = select i1 %cmp1, i32 %a, i32 %y
%cond5 = select i1 %cmp, i32 %cond, i32 %x
ret i32 %cond5
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: cmpl
; CHECK: cmov
; CHECK: cmov
define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movl $12, %eax
; CHECK-NEXT: btl
; CHECK-NEXT: cmovael (%rcx), %eax
}
define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl $12, %eax
; CHECK-NEXT: btl
; CHECK-NEXT: cmovbl (%rcx), %eax
declare void @bar(i64) nounwind
define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmovnel %edi, %esi
; CHECK-NEXT: movl %esi, %edi
%4 = load volatile i8* @g_100, align 1 ; <i8> [#uses=0]
br label %func_4.exit.i
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: g_100
; CHECK: testb
; CHECK-NOT: xor
; rdar://6668608
define i32 @test5(i32* nocapture %P) nounwind readonly {
entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: setg %al
; CHECK: movzbl %al, %eax
; CHECK: orl $-2, %eax
define i32 @test6(i32* nocapture %P) nounwind readonly {
entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: setl %al
; CHECK: movzbl %al, %eax
; CHECK: leal 4(%rax,%rax,8), %eax
; Don't try to use a 16-bit conditional move to do an 8-bit select,
; because it isn't worth it. Just use a branch instead.
define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: testb $1, %dil
; CHECK-NEXT: jne LBB
ReturnBlock: ; preds = %0
ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: cmpl $0, (%rsi)
}
ReturnBlock: ; preds = %0
ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl (%rsi), %eax
; CHECK: shll $3, %eax
; CHECK: testl %eax, %eax
%t = icmp eq i64 %x, 0
%r = zext i1 %t to i64
ret i64 %r
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: testq %rdi, %rdi
; CHECK: sete %al
; CHECK: movzbl %al, %eax
%t = icmp slt i64 %x, 1
%r = zext i1 %t to i64
ret i64 %r
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: testq %rdi, %rdi
; CHECK: setle %al
; CHECK: movzbl %al, %eax
bb12:; preds = %entry
ret i32 32
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: ucomisd LCPI4_0(%rip), %xmm0
; CHECK: ucomisd LCPI4_1(%rip), %xmm0
}
F:
ret i32 0
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: cmpq $0, -8(%rsp)
; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
}
; rdar://11866926
define i32 @test7(i64 %res) nounwind {
entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: sete
define i32 @test8(i64 %res) nounwind {
entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: cmpq $3, %rdi
define i32 @test9(i64 %res) nounwind {
entry:
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK-NOT: movabsq
; CHECK: shrq $33, %rdi
; CHECK: sete
define i32 @test10(i64 %res) nounwind {
entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: setne
; rdar://9758774
define i32 @test11(i64 %l) nounwind {
entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK-NOT: movabsq
; CHECK-NOT: andq
; CHECK: shrq $47, %rdi
}
define i32 @test12() uwtable ssp {
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: testb
%1 = call zeroext i1 @test12b()
br i1 %1, label %2, label %3
%inc = zext i1 %not.cmp to i32
%retval.0 = add i32 %inc, %b
ret i32 %retval.0
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: cmpl $1
; CHECK: sbbl $-1
; CHECK: ret
%inc = zext i1 %cmp to i32
%retval.0 = add i32 %inc, %b
ret i32 %retval.0
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: cmpl $1
; CHECK: adcl $0
; CHECK: ret
%inc = zext i1 %cmp to i32
%retval.0 = add i32 %inc, %b
ret i32 %retval.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpl $1
; CHECK: adcl $0
; CHECK: ret
%inc = zext i1 %not.cmp to i32
%retval.0 = add i32 %inc, %b
ret i32 %retval.0
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: cmpl $1
; CHECK: sbbl $-1
; CHECK: ret
%inc = zext i1 %not.cmp to i32
%retval.0 = sub i32 %b, %inc
ret i32 %retval.0
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: cmpl $1
; CHECK: adcl $-1
; CHECK: ret
%inc = zext i1 %cmp to i32
%retval.0 = sub i32 %b, %inc
ret i32 %retval.0
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: cmpl $1
; CHECK: sbbl $0
; CHECK: ret
%inc = zext i1 %cmp to i32
%retval.0 = sub i32 %b, %inc
ret i32 %retval.0
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: cmpl $1
; CHECK: sbbl $0
; CHECK: ret
%inc = zext i1 %not.cmp to i32
%retval.0 = sub i32 %b, %inc
ret i32 %retval.0
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: cmpl $1
; CHECK: adcl $-1
; CHECK: ret
ret i16 %call1
}
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: testb %dil, %dil
; CHECK: jne LBB0_2
; CHECK: divl
%cmp = icmp ugt i32 %cast, 1
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: leaq -1([[A0:%rdi|%rcx]])
; CHECK-NEXT: testq
; CHECK-NEXT: setne
%cmp = icmp ult i64 %count, 2
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: leaq -1([[A0]])
; CHECK-NEXT: testq
; CHECK-NEXT: sete
%cmp = icmp ult i6 %cast, 2
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpb $2
; CHECK: ret
}
; PR3018
define i32 @test(i32 %A) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: orl $1
; CHECK: ret
; Shows a dag combine bug that will generate an illegal build vector
; with v2i64 build_vector i32, i32.
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: unpcklpd
; CHECK: movapd
define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
ret void
}
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movdqa
define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
entry:
; verify-machineinstrs should ensure that DEBUG_VALUEs go before the
; terminator.
;
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: ##DEBUG_VALUE: i
%a = type { i32, i32 }
entry:
%div = udiv i16 %x, 33
ret i16 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: imull $63551, %eax, %eax
; CHECK-NEXT: shrl $21, %eax
; CHECK-NEXT: ret
%div = udiv i16 %c, 3
ret i16 %div
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: imull $43691, %eax, %eax
; CHECK-NEXT: shrl $17, %eax
; CHECK-NEXT: ret
%div = udiv i8 %c, 3
ret i8 %div
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movzbl 8(%esp), %eax
; CHECK-NEXT: imull $171, %eax, %eax
; CHECK-NEXT: shrl $9, %eax
entry:
%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
ret i16 %div
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: imull $1986, %eax, %
}
define i32 @test5(i32 %A) nounwind {
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
ret i32 %tmp1
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: movl $365384439, %eax
; CHECK: mull 4(%esp)
}
entry:
%div = sdiv i16 %x, 10
ret i16 %div
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: imull $26215, %eax, %ecx
; CHECK: sarl $18, %ecx
; CHECK: shrl $15, %eax
define i32 @test7(i32 %x) nounwind {
%div = udiv i32 %x, 28
ret i32 %div
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: shrl $2
; CHECK: movl $613566757
; CHECK: mull
define i8 @test8(i8 %x) nounwind {
%div = udiv i8 %x, 78
ret i8 %div
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: shrb %
; CHECK: imull $211
; CHECK: shrl $13
define i8 @test9(i8 %x) nounwind {
%div = udiv i8 %x, 116
ret i8 %div
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: shrb $2
; CHECK: imull $71
; CHECK: shrl $11
declare x86_fp80 @fabsl(x86_fp80)
-; CHECK: test1:
-; UNSAFE: test1:
-; NOOPT: test1:
+; CHECK-LABEL: test1:
+; UNSAFE-LABEL: test1:
+; NOOPT-LABEL: test1:
define float @test1(float %X) {
%Y = call float @fabsf(float %X) readnone
ret float %Y
; UNSAFE-NOT: fabs
; NOOPT-NOT: fabsf
-; CHECK: test2:
-; UNSAFE: test2:
-; NOOPT: test2:
+; CHECK-LABEL: test2:
+; UNSAFE-LABEL: test2:
+; NOOPT-LABEL: test2:
define double @test2(double %X) {
%Y = fcmp oge double %X, -0.0
%Z = fsub double -0.0, %X
; UNSAFE-NOT: fabs
-; CHECK: test3:
-; UNSAFE: test3:
-; NOOPT: test3:
+; CHECK-LABEL: test3:
+; UNSAFE-LABEL: test3:
+; NOOPT-LABEL: test3:
define x86_fp80 @test3(x86_fp80 %X) {
%Y = call x86_fp80 @fabsl(x86_fp80 %X) readnone
ret x86_fp80 %Y
ret i32 1
BB2:
ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: calll
; CHECK-NEXT: testb $1
}
define void @test2(%struct.s* %d) nounwind {
call void @foo2(%struct.s* byval %d )
ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl (%eax)
; CHECK: movl {{.*}}, (%esp)
; CHECK: movl 4(%eax)
define void @test3(i8* %a) {
call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false)
ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movl {{.*}}, (%esp)
; CHECK: movl $0, 4(%esp)
; CHECK: movl $100, 8(%esp)
define void @test4(i8* %a, i8* %b) {
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false)
ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movl {{.*}}, (%esp)
; CHECK: movl {{.*}}, 4(%esp)
; CHECK: movl $100, 8(%esp)
ret i64 %result
}
-; CHECK: test_sdiv64:
+; CHECK-LABEL: test_sdiv64:
; CHECK: cqto
; CHECK: idivq
ret i64 %result
}
-; CHECK: test_srem64:
+; CHECK-LABEL: test_srem64:
; CHECK: cqto
; CHECK: idivq
ret i64 %result
}
-; CHECK: test_udiv64:
+; CHECK-LABEL: test_udiv64:
; CHECK: xorl
; CHECK: divq
ret i64 %result
}
-; CHECK: test_urem64:
+; CHECK-LABEL: test_urem64:
; CHECK: xorl
; CHECK: divq
ret i8 %result
}
-; CHECK: test_sdiv8:
+; CHECK-LABEL: test_sdiv8:
; CHECK: movsbw
; CHECK: idivb
ret i8 %result
}
-; CHECK: test_srem8:
+; CHECK-LABEL: test_srem8:
; CHECK: movsbw
; CHECK: idivb
ret i8 %result
}
-; CHECK: test_udiv8:
+; CHECK-LABEL: test_udiv8:
; CHECK: movzbw
; CHECK: divb
ret i8 %result
}
-; CHECK: test_urem8:
+; CHECK-LABEL: test_urem8:
; CHECK: movzbw
; CHECK: divb
ret i16 %result
}
-; CHECK: test_sdiv16:
+; CHECK-LABEL: test_sdiv16:
; CHECK: cwtd
; CHECK: idivw
ret i16 %result
}
-; CHECK: test_srem16:
+; CHECK-LABEL: test_srem16:
; CHECK: cwtd
; CHECK: idivw
ret i16 %result
}
-; CHECK: test_udiv16:
+; CHECK-LABEL: test_udiv16:
; CHECK: xorl
; CHECK: divw
ret i16 %result
}
-; CHECK: test_urem16:
+; CHECK-LABEL: test_urem16:
; CHECK: xorl
; CHECK: divw
ret i32 %result
}
-; CHECK: test_sdiv32:
+; CHECK-LABEL: test_sdiv32:
; CHECK: cltd
; CHECK: idivl
ret i32 %result
}
-; CHECK: test_srem32:
+; CHECK-LABEL: test_srem32:
; CHECK: cltd
; CHECK: idivl
ret i32 %result
}
-; CHECK: test_udiv32:
+; CHECK-LABEL: test_udiv32:
; CHECK: xorl
; CHECK: divl
ret i32 %result
}
-; CHECK: test_urem32:
+; CHECK-LABEL: test_urem32:
; CHECK: xorl
; CHECK: divl
%4 = add i64 %3, 10
store i64 %4, i64* %0
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: callq _f
; CHECK-NEXT: addq $10, %rax
}
%4 = add i64 %3, 10
store i64 %4, i64* %0
ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: callq _f
; CHECK-NEXT: addq $10, %rdx
}
%t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1]
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
-; X32: test1:
+; X32-LABEL: test1:
; X32: movl (%eax,%ecx,4), %eax
; X32: ret
-; X64: test1:
+; X64-LABEL: test1:
; X64: movslq %e[[A0:di|cx]], %rax
; X64: movl (%r[[A1:si|dx]],%rax,4), %eax
; X64: ret
%t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1]
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
-; X32: test2:
+; X32-LABEL: test2:
; X32: movl (%edx,%ecx,4), %e
; X32: ret
-; X64: test2:
+; X64-LABEL: test2:
; X64: movl (%r[[A1]],%r[[A0]],4), %eax
; X64: ret
}
ret i8 %B
-; X32: test3:
+; X32-LABEL: test3:
; X32: movl 4(%esp), %eax
; X32: movb -2(%eax), %al
; X32: ret
-; X64: test3:
+; X64-LABEL: test3:
; X64: movb -2(%r[[A0]]), %al
; X64: ret
%tmp2 = load double* %arrayidx ; <double> [#uses=1]
ret double %tmp2
-; X32: test4:
+; X32-LABEL: test4:
; X32: 128(%e{{.*}},%e{{.*}},8)
-; X64: test4:
+; X64-LABEL: test4:
; X64: 128(%r{{.*}},%r{{.*}},8)
}
%v10 = load i64* %v9
%v11 = add i64 %B, %v10
ret i64 %v11
-; X64: test5:
+; X64-LABEL: test5:
; X64: movslq %e[[A1]], %rax
; X64-NEXT: (%r[[A0]],%rax),
; X64: ret
; PR10605 / rdar://9930964 - Don't fold loads incorrectly. The load should
; happen before the store.
define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind {
-; X64: test7:
+; X64-LABEL: test7:
; X64: movl 8({{%rdi|%rcx}}), %eax
; X64: movl $4, 8({{%rdi|%rcx}})
declare i32 @test1a(i32)
define i32 @test1(i32 %x) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: andb $1, %
%y = add i32 %x, -3
%t = call i32 @test1a(i32 %y)
define void @test2(i8* %a) nounwind {
entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movb {{.*}} %al
; CHECK-NEXT: xorb $1, %al
; CHECK-NEXT: testb $1
ret i32 %and
}
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: andl $8,
if.end: ; preds = %if.then, %entry
ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movq %rdi, -8(%rsp)
; CHECK: cmpq $42, -8(%rsp)
}
define i64 @test3() nounwind {
%A = ptrtoint i32* @G to i64
ret i64 %A
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movq _G@GOTPCREL(%rip), %rax
; CHECK-NEXT: ret
}
%conv = zext i8 %tmp11 to i32
ret i32 %conv
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax
; CHECK-NEXT: movzbl (%rax,%rdi), %eax
; CHECK-NEXT: ret
store i32 %y, i32* %p
ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: movl $50000, %ecx
; CHECK: sarl %cl, %edi
; CHECK: ret
%mul = mul nsw i64 %x, 8
ret i64 %mul
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: shlq $3, %rdi
}
entry:
%mul = mul nsw i32 %x, 8
ret i32 %mul
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: shll $3, %edi
}
%add = add nsw i64 %x, 7
ret i64 %add
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: addq $7, %rdi
}
entry:
%add = mul nsw i64 %x, 7
ret i64 %add
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: imulq $7, %rdi, %rax
}
define i32 @test10(i32 %X) nounwind {
%Y = udiv i32 %X, 8
ret i32 %Y
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: shrl $3,
}
define i32 @test11(i32 %X) nounwind {
%Y = sdiv exact i32 %X, 8
ret i32 %Y
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: sarl $3,
}
if.end: ; preds = %if.then, %entry
ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: testb $1,
; CHECK-NEXT: je L
; CHECK-NEXT: movl $0, %edi
define void @test13() nounwind {
call void @test13f(i1 0)
ret void
-; CHECK: test13:
+; CHECK-LABEL: test13:
; CHECK: movl $0, %edi
; CHECK-NEXT: callq
}
%tobool = trunc i8 %tmp to i1
call void @test13f(i1 zeroext %tobool) noredzone
ret void
-; CHECK: test14:
+; CHECK-LABEL: test14:
; CHECK: andb $1,
; CHECK: callq
}
define void @test15(i8* %a, i8* %b) nounwind {
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false)
ret void
-; CHECK: test15:
+; CHECK-LABEL: test15:
; CHECK-NEXT: movl (%rsi), %eax
; CHECK-NEXT: movl %eax, (%rdi)
; CHECK-NEXT: ret
; Handling for varargs calls
declare void @test16callee(...) nounwind
define void @test16() nounwind {
-; CHECK: test16:
+; CHECK-LABEL: test16:
; CHECK: movl $1, %edi
; CHECK: movb $0, %al
; CHECK: callq _test16callee
if.else: ; preds = %entry
ret i32 2
-; CHECK: test17:
+; CHECK-LABEL: test17:
; CHECK: movl (%rdi), %eax
; CHECK: callq _foo
; CHECK: cmpl $5, %eax
define void @test18(float* %p1) {
store float 0.0, float* %p1
ret void
-; CHECK: test18:
+; CHECK-LABEL: test18:
; CHECK: xorps
}
define void @test19(double* %p1) {
store double 0.0, double* %p1
ret void
-; CHECK: test19:
+; CHECK-LABEL: test19:
; CHECK: xorps
}
%tmp = alloca %struct.a, align 8
call void @test20sret(%struct.a* sret %tmp)
ret void
-; CHECK: test20:
+; CHECK-LABEL: test20:
; CHECK: leaq (%rsp), %rdi
; CHECK: callq _test20sret
}
define void @test21(double* %p1) {
store double -0.0, double* %p1
ret void
-; CHECK: test21:
+; CHECK-LABEL: test21:
; CHECK-NOT: xor
; CHECK: movsd LCPI
}
call void @foo22(i32 2)
call void @foo22(i32 3)
ret void
-; CHECK: test22:
+; CHECK-LABEL: test22:
; CHECK: movl $0, %edi
; CHECK: callq _foo22
; CHECK: movl $1, %edi
%a = alloca i8
%b = call i8* @foo23()
ret void
-; CHECK: test23:
+; CHECK-LABEL: test23:
; CHECK: call
; CHECK: movq %rdi, %rax
; CHECK: ret
; RUN: llc -fast-isel -O0 -mcpu=generic -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s
; This should use flds to set the return value.
-; CHECK: test0:
+; CHECK-LABEL: test0:
; CHECK: flds
; CHECK: ret
@G = external global float
}
; This should pop 4 bytes on return.
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: ret $4
define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p
}
; Properly initialize the pic base.
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK-NOT: HHH
; CHECK: call{{.*}}L2$pb
; CHECK-NEXT: L2$pb:
%tmp = alloca %struct.a, align 8
call void @test3sret(%struct.a* sret %tmp)
ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: subl $44
; CHECK: leal 16(%esp)
; CHECK: calll _test3sret
%tmp = alloca %struct.a, align 8
call fastcc void @test4fastccsret(%struct.a* sret %tmp)
ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: subl $28
; CHECK: leal (%esp), %ecx
; CHECK: calll _test4fastccsret
store i16 %A, i16* %Q
ret i32 %D
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl 4(%esp), %eax
; CHECK-NEXT: movzwl (%eax), %ecx
; rdar://10554090
; xor in exit block will be CSE'ed and load will be folded to xor in entry.
define i1 @test3(i32* %P, i32* %Q) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movl 8(%esp), %eax
; CHECK: xorl (%eax),
; CHECK: j
;; ret
; rdar://10695237
define i32 @test(i32 %a) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: mov
; CHECK-NEXT: neg
; CHECK-NEXT: cmov
; RUN: llc < %s -march=x86 | FileCheck %s
define i32 @test(i32* %X, i32 %B) {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK-NOT: lea
; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4)
@a = common global i32 0, align 4
define i32 @test1(i32 %p1) nounwind uwtable {
entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: testb
; CHECK: j
; CHECK: ret
%tmp1 = shl i32 %x, 3
%tmp2 = add i32 %tmp1, 7
ret i32 %tmp2
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: leal 7(,%r[[A0:di|cx]],8), %eax
}
bb2:
ret i32 %x_offs
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl %e[[A0]], %eax
; CHECK: addl $-5, %eax
; CHECK: andl $-4, %eax
%sh_prom = zext i32 %and to i64
%shl = shl i64 %conv, %sh_prom
ret i64 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: shll %cl, %eax
; CHECK: shrl %edx
; CHECK: xorb $31
%sh_prom = zext i32 %and to i64
%shl = shl i64 %xx, %sh_prom
ret i64 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: shll %cl, %esi
; CHECK: shrl %edx
; CHECK: xorb $31
%sh_prom = zext i32 %and to i64
%shr = lshr i64 %xx, %sh_prom
ret i64 %shr
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: shrl %cl, %esi
; CHECK: leal (%edx,%edx), %eax
; CHECK: xorb $31, %cl
%sh_prom = zext i32 %and to i64
%shr = ashr i64 %xx, %sh_prom
ret i64 %shr
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: shrl %cl, %esi
; CHECK: leal (%edx,%edx), %eax
; CHECK: xorb $31, %cl
; This should not load or store the top part of *P.
define void @test(i64* %P) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: movl 4(%esp), %[[REGISTER:.*]]
; CHECK-NOT: 4(%[[REGISTER]])
; CHECK: ret
; we don't want to leave extra induction variables around, or use an
; lea to compute an exit condition inside the loop:
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: BB10_4:
; CHECK-NEXT: movaps %xmm{{.*}}, %xmm{{.*}}
tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %b, i64 %n, i32 1, i1 0 )
ret i8* %a
-; LINUX: test1:
+; LINUX-LABEL: test1:
; LINUX: memcpy
}
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8, i1 0 )
ret i8* %tmp14
-; LINUX: test2:
+; LINUX-LABEL: test2:
; LINUX: memcpy
}
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
; LINUX: memcpy
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
; DARWIN-NOT: memcpy
; DARWIN: movq
; DARWIN: movq
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
; LINUX: movq
; LINUX: movq
; LINUX: movq
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false)
ret void
-; DARWIN: test5:
+; DARWIN-LABEL: test5:
; DARWIN: movabsq $7016996765293437281
; DARWIN: movabsq $7016996765293437184
}
call void @dummy(i8* %x)
ret void
-; NOSSE: test1:
+; NOSSE-LABEL: test1:
; NOSSE-NOT: and
; NOSSE: movl $0
-; SSE1: test1:
+; SSE1-LABEL: test1:
; SSE1: andl $-16
; SSE1: movl %esp, %esi
; SSE1: movaps
-; SSE2: test1:
+; SSE2-LABEL: test1:
; SSE2: andl $-16
; SSE2: movl %esp, %esi
; SSE2: movaps
-; AVX1: test1:
+; AVX1-LABEL: test1:
; AVX1: andl $-32
; AVX1: movl %esp, %esi
; AVX1: vmovaps %ymm
-; AVX2: test1:
+; AVX2-LABEL: test1:
; AVX2: andl $-32
; AVX2: movl %esp, %esi
; AVX2: vmovaps %ymm
call void @dummy(i8* %x)
ret void
-; NOSSE: test2:
+; NOSSE-LABEL: test2:
; NOSSE-NOT: and
; NOSSE: movl $0
-; SSE1: test2:
+; SSE1-LABEL: test2:
; SSE1: andl $-16
; SSE1: movl %esp, %esi
; SSE1: movaps
-; SSE2: test2:
+; SSE2-LABEL: test2:
; SSE2: andl $-16
; SSE2: movl %esp, %esi
; SSE2: movaps
-; AVX1: test2:
+; AVX1-LABEL: test2:
; AVX1: andl $-16
; AVX1: movl %esp, %esi
; AVX1: vmovaps %xmm
-; AVX2: test2:
+; AVX2-LABEL: test2:
; AVX2: andl $-16
; AVX2: movl %esp, %esi
; AVX2: vmovaps %xmm
%bswap = call i32 @llvm.bswap.i32(i32 %y)
store i32 %bswap, i32* %x, align 4
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movbel %esi, (%rdi)
}
%load = load i32* %x, align 4
%bswap = call i32 @llvm.bswap.i32(i32 %load)
ret i32 %bswap
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movbel (%rdi), %eax
}
%bswap = call i64 @llvm.bswap.i64(i64 %y)
store i64 %bswap, i64* %x, align 8
ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movbeq %rsi, (%rdi)
}
%load = load i64* %x, align 8
%bswap = call i64 @llvm.bswap.i64(i64 %load)
ret i64 %bswap
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movbeq (%rdi), %rax
}
%tmp1 = load i32* %tmp ; <i32> [#uses=1]
ret i32 %tmp1
}
-; X32: test1:
+; X32-LABEL: test1:
; X32: movl %gs:196, %eax
; X32: movl (%eax), %eax
; X32: ret
-; X64: test1:
+; X64-LABEL: test1:
; X64: movq %gs:320, %rax
; X64: movl (%rax), %eax
; X64: ret
}
; rdar://8453210
-; X32: test2:
+; X32-LABEL: test2:
; X32: movl {{.*}}(%esp), %eax
; X32: calll *%gs:(%eax)
-; X64: test2:
+; X64-LABEL: test2:
; X64: callq *%gs:([[A0:%rdi|%rcx]])
%tmp4 = add i32 %tmp1, %tmp3
ret i32 %tmp4
}
-; X32: test_no_cse:
+; X32-LABEL: test_no_cse:
; X32: movl %gs:196
; X32: movl %fs:196
; X32: ret
%and = shl i32 %x, 10
%shl = and i32 %and, 31744
ret i32 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: andl $31
; CHECK: shll $10
}
%or = shl i32 %x, 10
%shl = or i32 %or, 31744
ret i32 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: orl $31
; CHECK: shll $10
}
%xor = shl i32 %x, 10
%shl = xor i32 %xor, 31744
ret i32 %shl
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: xorl $31
; CHECK: shll $10
}
%and = shl i64 %x, 40
%shl = and i64 %and, 264982302294016
ret i64 %shl
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: andq $241
; CHECK: shlq $40
}
%and = shl i64 %x, 40
%shl = and i64 %and, 34084860461056
ret i64 %shl
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: andq $31
; CHECK: shlq $40
}
%and = shl i64 %x, 32
%shl = and i64 %and, -281474976710656
ret i64 %shl
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: andq $-65536
; CHECK: shlq $32
}
%or = shl i64 %x, 40
%shl = or i64 %or, 264982302294016
ret i64 %shl
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: orq $241
; CHECK: shlq $40
}
%or = shl i64 %x, 40
%shl = or i64 %or, 34084860461056
ret i64 %shl
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: orq $31
; CHECK: shlq $40
}
%xor = shl i64 %x, 40
%shl = xor i64 %xor, 264982302294016
ret i64 %shl
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: orq $241
; CHECK: shlq $40
}
%xor = shl i64 %x, 40
%shl = xor i64 %xor, 34084860461056
ret i64 %shl
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: xorq $31
; CHECK: shlq $40
}
%xor = shl i64 %x, 33
%shl = xor i64 %xor, -562949953421312
ret i64 %shl
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: xorq $-65536
; CHECK: shlq $33
}
; DAGCombiner shouldn't fold the sdiv (ashr) away.
; rdar://8636812
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: sarl
define i32 @test2() nounwind {
%retval.0 = select i1 %tobool, i32 1, i32 %cmp
ret i32 %retval.0
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: cmov
}
ret void
}
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: pshufd
; CHECK-YONAH: pshufd
%C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 >
}
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: palignr
; CHECK-YONAH: shufps
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 >
}
define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: palignr
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
ret <4 x i32> %C
}
define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: palignr
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
ret <4 x i32> %C
}
define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: palignr
%C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
ret <4 x float> %C
}
define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: palignr
%C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 >
ret <8 x i16> %C
}
define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: palignr
%C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 >
ret <8 x i16> %C
}
define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: palignr
%C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 >
ret <16 x i8> %C
; incorrectly. In particular, one of the operands of the palignr node
; was an UNDEF.)
define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK-NOT: palignr
; CHECK: pshufb
%C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
%cond = zext i1 %cmp to i8
%add = add i8 %cond, %b
ret i8 %add
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: adcb $0
}
%cond = zext i1 %cmp to i32
%add = add i32 %cond, %b
ret i32 %add
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: adcl $0
}
%conv = zext i1 %cmp to i64
%add = add i64 %conv, %b
ret i64 %add
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: adcq $0
}
%cond = zext i1 %cmp to i8
%sub = sub i8 %b, %cond
ret i8 %sub
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: sbbb $0
}
%cond = zext i1 %cmp to i32
%sub = sub i32 %b, %cond
ret i32 %sub
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: sbbl $0
}
%conv = zext i1 %cmp to i64
%sub = sub i64 %b, %conv
ret i64 %sub
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: sbbq $0
}
%cond = sext i1 %cmp to i8
%sub = sub i8 %b, %cond
ret i8 %sub
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: adcb $0
}
%cond = sext i1 %cmp to i32
%sub = sub i32 %b, %cond
ret i32 %sub
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: adcl $0
}
%conv = sext i1 %cmp to i64
%sub = sub i64 %b, %conv
ret i64 %sub
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: adcq $0
}
; Just like @and, but without the trunc+store. This should use a testb
; instead of an andl.
-; CHECK: test:
+; CHECK-LABEL: test:
define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
entry:
store i8 0, i8* %p
store i32 %tmp.s, i32* @dst
ret void
-; LINUX: test0:
+; LINUX-LABEL: test0:
; LINUX: calll .L0$pb
; LINUX-NEXT: .L0$pb:
; LINUX-NEXT: popl
store i32 %tmp.s, i32* @dst2
ret void
-; LINUX: test1:
+; LINUX-LABEL: test1:
; LINUX: calll .L1$pb
; LINUX-NEXT: .L1$pb:
; LINUX-NEXT: popl
entry:
%ptr = call i8* @malloc(i32 40)
ret void
-; LINUX: test2:
+; LINUX-LABEL: test2:
; LINUX: pushl %ebx
; LINUX-NEXT: subl $8, %esp
; LINUX-NEXT: calll .L2$pb
%tmp1 = load void(...)** @pfoo
call void(...)* %tmp1()
ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
; LINUX: calll .L3$pb
; LINUX-NEXT: .L3$pb:
; LINUX: popl
entry:
call void(...)* @foo()
ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
; LINUX: calll .L4$pb
; LINUX: popl %ebx
; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx
store i32 %tmp.s, i32* @dst6
ret void
-; LINUX: test5:
+; LINUX-LABEL: test5:
; LINUX: calll .L5$pb
; LINUX-NEXT: .L5$pb:
; LINUX-NEXT: popl %eax
; LINUX: .LCPI6_0:
-; LINUX: test6:
+; LINUX-LABEL: test6:
; LINUX: calll .L6$pb
; LINUX: .L6$pb:
; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb),
tail call void(...)* @foo6()
ret void
-; LINUX: test7:
+; LINUX-LABEL: test7:
; LINUX: calll .L7$pb
; LINUX: .L7$pb:
; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb),
store <2 x i64> %sext, <2 x i64>* %out, align 8
ret void
-; SSE41: test1:
+; SSE41-LABEL: test1:
; SSE41: pmovsxbq
-; AVX1: test1:
+; AVX1-LABEL: test1:
; AVX1: vpmovsxbq
-; AVX2: test1:
+; AVX2-LABEL: test1:
; AVX2: vpmovsxbq
}
store <4 x i64> %sext, <4 x i64>* %out, align 8
ret void
-; AVX2: test2:
+; AVX2-LABEL: test2:
; AVX2: vpmovsxbq
}
store <4 x i32> %sext, <4 x i32>* %out, align 8
ret void
-; SSE41: test3:
+; SSE41-LABEL: test3:
; SSE41: pmovsxbd
-; AVX1: test3:
+; AVX1-LABEL: test3:
; AVX1: vpmovsxbd
-; AVX2: test3:
+; AVX2-LABEL: test3:
; AVX2: vpmovsxbd
}
store <8 x i32> %sext, <8 x i32>* %out, align 8
ret void
-; AVX2: test4:
+; AVX2-LABEL: test4:
; AVX2: vpmovsxbd
}
store <8 x i16> %sext, <8 x i16>* %out, align 8
ret void
-; SSE41: test5:
+; SSE41-LABEL: test5:
; SSE41: pmovsxbw
-; AVX1: test5:
+; AVX1-LABEL: test5:
; AVX1: vpmovsxbw
-; AVX2: test5:
+; AVX2-LABEL: test5:
; AVX2: vpmovsxbw
}
store <16 x i16> %sext, <16 x i16>* %out, align 8
ret void
-; AVX2: test6:
+; AVX2-LABEL: test6:
; FIXME: v16i8 -> v16i16 is scalarized.
; AVX2-NOT: pmovsx
}
ret void
-; SSE41: test7:
+; SSE41-LABEL: test7:
; SSE41: pmovsxwq
-; AVX1: test7:
+; AVX1-LABEL: test7:
; AVX1: vpmovsxwq
-; AVX2: test7:
+; AVX2-LABEL: test7:
; AVX2: vpmovsxwq
}
store <4 x i64> %sext, <4 x i64>* %out, align 8
ret void
-; AVX2: test8:
+; AVX2-LABEL: test8:
; AVX2: vpmovsxwq
}
store <4 x i32> %sext, <4 x i32>* %out, align 8
ret void
-; SSE41: test9:
+; SSE41-LABEL: test9:
; SSE41: pmovsxwd
-; AVX1: test9:
+; AVX1-LABEL: test9:
; AVX1: vpmovsxwd
-; AVX2: test9:
+; AVX2-LABEL: test9:
; AVX2: vpmovsxwd
}
store <8 x i32> %sext, <8 x i32>* %out, align 8
ret void
-; AVX2: test10:
+; AVX2-LABEL: test10:
; AVX2: vpmovsxwd
}
store <2 x i64> %sext, <2 x i64>* %out, align 8
ret void
-; SSE41: test11:
+; SSE41-LABEL: test11:
; SSE41: pmovsxdq
-; AVX1: test11:
+; AVX1-LABEL: test11:
; AVX1: vpmovsxdq
-; AVX2: test11:
+; AVX2-LABEL: test11:
; AVX2: vpmovsxdq
}
store <4 x i64> %sext, <4 x i64>* %out, align 8
ret void
-; AVX2: test12:
+; AVX2-LABEL: test12:
; AVX2: vpmovsxdq
}
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NEXT: pmulld
-; WIN64: test1:
+; WIN64-LABEL: test1:
; WIN64-NEXT: movdqa (%rcx), %xmm0
; WIN64-NEXT: pmulld (%rdx), %xmm0
%C = mul <4 x i32> %A, %B
}
define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind {
-; CHECK: test1a:
+; CHECK-LABEL: test1a:
; CHECK-NEXT: pmulld
-; WIN64: test1a:
+; WIN64-LABEL: test1a:
; WIN64-NEXT: movdqa (%rcx), %xmm0
; WIN64-NEXT: pmulld (%rdx), %xmm0
define void @test3() nounwind ssp {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: decq 16(%rax)
%0 = load i64** @foo, align 8
%arrayidx = getelementptr inbounds i64* %0, i64 2
; Make sure at end of do.cond.i, we jump to do.body.i first to have a tighter
; inner loop.
define i32 @test_branches_order() uwtable ssp {
-; CHECK: test_branches_order:
+; CHECK-LABEL: test_branches_order:
; CHECK: [[L0:LBB0_[0-9]+]]: ## %do.body.i
; CHECK: je
; CHECK: %do.cond.i
define i32 @test1(i32 %x) {
%div = sdiv exact i32 %x, 25
ret i32 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: imull $-1030792151, 4(%esp)
; CHECK-NEXT: ret
}
define i32 @test2(i32 %x) {
%div = sdiv exact i32 %x, 24
ret i32 %div
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: sarl $3
; CHECK-NEXT: imull $-1431655765
; CHECK-NEXT: ret
%retvalue = call i32 @test_basic(i32 %newlen)
ret i32 %retvalue
-; X32: test_basic:
+; X32-LABEL: test_basic:
; X32: cmpl %gs:48, %esp
; X32-NEXT: ja .LBB0_2
; X32-NEXT: calll __morestack_allocate_stack_space
; X32-NEXT: addl $16, %esp
-; X64: test_basic:
+; X64-LABEL: test_basic:
; X64: cmpq %fs:112, %rsp
; X64-NEXT: ja .LBB0_2
%t4 = select i1 %r, %0 %t0, %0 %t1
%t5 = extractvalue %0 %t4, 1
ret i32 %t5
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: cmovneq %rdi, %rsi
; CHECK: movl (%rsi), %eax
-; ATOM: test1:
+; ATOM-LABEL: test1:
; ATOM: cmovneq %rdi, %rsi
; ATOM: movl (%rsi), %eax
}
unreachable
bb91: ; preds = %bb84
ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movnew
; CHECK: movswl
-; ATOM: test2:
+; ATOM-LABEL: test2:
; ATOM: movnew
; ATOM: movswl
}
%0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
%iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01 ; <float> [#uses=1]
ret float %iftmp.0.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: movss {{.*}},4), %xmm0
-; ATOM: test3:
+; ATOM-LABEL: test3:
; ATOM: movss {{.*}},4), %xmm0
}
%1 = getelementptr i8* %P, i32 %iftmp.0.0 ; <i8*> [#uses=1]
%2 = load i8* %1, align 1 ; <i8> [#uses=1]
ret i8 %2
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movsbl ({{.*}},4), %eax
-; ATOM: test4:
+; ATOM-LABEL: test4:
; ATOM: movsbl ({{.*}},4), %eax
}
%x = select i1 %c, <2 x i16> %a, <2 x i16> %b
store <2 x i16> %x, <2 x i16>* %p
ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
-; ATOM: test5:
+; ATOM-LABEL: test5:
}
define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
ret void
; Verify that the fmul gets sunk into the one part of the diamond where it is
; needed.
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: je
; CHECK: ret
; CHECK: mulps
; CHECK: ret
-; ATOM: test6:
+; ATOM-LABEL: test6:
; ATOM: je
; ATOM: ret
; ATOM: mulps
%tmp9 = icmp sgt i32 %tmp8, -1 ; <i1> [#uses=1]
%retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
ret x86_fp80 %retval
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: leaq
; CHECK: fldt (%r{{.}}x,%r{{.}}x)
-; ATOM: test7:
+; ATOM-LABEL: test7:
; ATOM: leaq
; ATOM: fldt (%r{{.}}x,%r{{.}}x)
}
store <6 x i32> %val, <6 x i32>* %dst.addr
ret void
-; CHECK: test8:
+; CHECK-LABEL: test8:
-; ATOM: test8:
+; ATOM-LABEL: test8:
}
%cmp = icmp ne i64 %x, 0
%cond = select i1 %cmp, i64 %y, i64 -1
ret i64 %cond
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: orq %rsi, %rax
; CHECK: ret
-; ATOM: test9:
+; ATOM-LABEL: test9:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: orq %rsi, %rax
%cmp = icmp eq i64 %x, 0
%cond = select i1 %cmp, i64 -1, i64 %y
ret i64 %cond
-; CHECK: test9a:
+; CHECK-LABEL: test9a:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: orq %rsi, %rax
; CHECK: ret
-; ATOM: test9a:
+; ATOM-LABEL: test9a:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: orq %rsi, %rax
%A = sext i1 %cmp to i64
%cond = or i64 %y, %A
ret i64 %cond
-; CHECK: test9b:
+; CHECK-LABEL: test9b:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: orq %rsi, %rax
; CHECK: ret
-; ATOM: test9b:
+; ATOM-LABEL: test9b:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: orq %rsi, %rax
%cmp = icmp eq i64 %x, 0
%cond = select i1 %cmp, i64 -1, i64 1
ret i64 %cond
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: orq $1, %rax
; CHECK: ret
-; ATOM: test10:
+; ATOM-LABEL: test10:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: orq $1, %rax
%cmp = icmp eq i64 %x, 0
%cond = select i1 %cmp, i64 %y, i64 -1
ret i64 %cond
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: notq %rax
; CHECK: orq %rsi, %rax
; CHECK: ret
-; ATOM: test11:
+; ATOM-LABEL: test11:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: notq %rax
%cmp = icmp ne i64 %x, 0
%cond = select i1 %cmp, i64 -1, i64 %y
ret i64 %cond
-; CHECK: test11a:
+; CHECK-LABEL: test11a:
; CHECK: cmpq $1, %rdi
; CHECK: sbbq %rax, %rax
; CHECK: notq %rax
; CHECK: orq %rsi, %rax
; CHECK: ret
-; ATOM: test11a:
+; ATOM-LABEL: test11a:
; ATOM: cmpq $1, %rdi
; ATOM: sbbq %rax, %rax
; ATOM: notq %rax
%D = select i1 %B, i64 -1, i64 %C
%call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
ret i8* %call
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: movq $-1, %rdi
; CHECK: mulq
; CHECK: cmovnoq %rax, %rdi
; CHECK: jmp __Znam
-; ATOM: test12:
+; ATOM-LABEL: test12:
; ATOM: mulq
; ATOM: movq $-1, %rdi
; ATOM: cmovnoq %rax, %rdi
%c = icmp ult i32 %a, %b
%d = sext i1 %c to i32
ret i32 %d
-; CHECK: test13:
+; CHECK-LABEL: test13:
; CHECK: cmpl
; CHECK-NEXT: sbbl
; CHECK-NEXT: ret
-; ATOM: test13:
+; ATOM-LABEL: test13:
; ATOM: cmpl
; ATOM-NEXT: sbbl
; ATOM: ret
%c = icmp uge i32 %a, %b
%d = sext i1 %c to i32
ret i32 %d
-; CHECK: test14:
+; CHECK-LABEL: test14:
; CHECK: cmpl
; CHECK-NEXT: sbbl
; CHECK-NEXT: notl
; CHECK-NEXT: ret
-; ATOM: test14:
+; ATOM-LABEL: test14:
; ATOM: cmpl
; ATOM-NEXT: sbbl
; ATOM-NEXT: notl
%cmp = icmp ne i32 %x, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK: test15:
+; CHECK-LABEL: test15:
; CHECK: negl
; CHECK: sbbl
-; ATOM: test15:
+; ATOM-LABEL: test15:
; ATOM: negl
; ATOM: sbbl
}
%cmp = icmp ne i64 %x, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK: test16:
+; CHECK-LABEL: test16:
; CHECK: negq
; CHECK: sbbq
-; ATOM: test16:
+; ATOM-LABEL: test16:
; ATOM: negq
; ATOM: sbbq
}
%cmp = icmp ne i16 %x, 0
%sub = sext i1 %cmp to i16
ret i16 %sub
-; CHECK: test17:
+; CHECK-LABEL: test17:
; CHECK: negw
; CHECK: sbbw
-; ATOM: test17:
+; ATOM-LABEL: test17:
; ATOM: negw
; ATOM: sbbw
}
%cmp = icmp slt i32 %x, 15
%sel = select i1 %cmp, i8 %a, i8 %b
ret i8 %sel
-; CHECK: test18:
+; CHECK-LABEL: test18:
; CHECK: cmpl $15, %edi
; CHECK: cmovgel %edx
-; ATOM: test18:
+; ATOM-LABEL: test18:
; ATOM: cmpl $15, %edi
; ATOM: cmovgel %edx
}
%retval.0 = select i1 %cmp, i64 2, i64 %add
ret i64 %retval.0
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: leaq 1(%rdi), %rax
; CHECK: cmpq $2, %rdi
; CHECK: cmoveq %rdi, %rax
; When doing sign extension, use the sext-load lowering to take advantage of
; x86's sign extension during loads.
;
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movsbl {{.*}}, %eax
; CHECK-NEXT: ret
define i32 @test1(i32 %X) nounwind {
; When using a sextload representation, ensure that the sign extension is
; preserved even when removing shifted-out low bits.
;
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movswl {{.*}}, %eax
; CHECK-NEXT: ret
define i32 @test2({i16, [6 x i8]}* %this) {
@array = weak global [4 x i32] zeroinitializer
define i32 @test_lshr_and(i32 %x) {
-; CHECK: test_lshr_and:
+; CHECK-LABEL: test_lshr_and:
; CHECK-NOT: shrl
; CHECK: andl $12,
; CHECK: movl {{.*}}array{{.*}},
; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s
define i32* @test1(i32* %P, i32 %X) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: shrl
; CHECK-NOT: shll
; CHECK: ret
}
define i32* @test2(i32* %P, i32 %X) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: shll $4
; CHECK-NOT: shll
; CHECK: ret
}
define i32* @test3(i32* %P, i32 %X) {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK-NOT: shrl
; CHECK-NOT: shll
; CHECK: ret
}
define fastcc i32 @test4(i32* %d) {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK-NOT: shrl
; CHECK: ret
define i64 @test5(i16 %i, i32* %arr) {
; Ensure that we don't fold away shifts which have multiple uses, as they are
; just re-introduced for the second use.
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK-NOT: shrl
; CHECK: shrl $11
; CHECK-NOT: shrl
if.end:
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: cmpb $47, (%{{rdi|rcx}})
}
if.end:
ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: cmpb $47, %{{dil|cl}}
}
if.end:
ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpb $-1, %{{dil|cl}}
}
if.end:
ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK-NOT: cmpl $1,{{.*}}x+4
; CHECK: ret
}
declare void @callee1(i32 inreg, i32 inreg, i32 inreg)
define void @test1(i32 %a, i32 %b) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: calll callee1@PLT
tail call void @callee1(i32 inreg 0, i32 inreg 0, i32 inreg 0) nounwind
ret void
define float @test1(float %x) nounwind {
entry:
-; GNU_SINCOS: test1:
+; GNU_SINCOS-LABEL: test1:
; GNU_SINCOS: callq sincosf
; GNU_SINCOS: movss 4(%rsp), %xmm0
; GNU_SINCOS: addss (%rsp), %xmm0
-; OSX_SINCOS: test1:
+; OSX_SINCOS-LABEL: test1:
; OSX_SINCOS: callq ___sincosf_stret
; OSX_SINCOS: pshufd $1, %xmm0, %xmm1
; OSX_SINCOS: addss %xmm0, %xmm1
define double @test2(double %x) nounwind {
entry:
-; GNU_SINCOS: test2:
+; GNU_SINCOS-LABEL: test2:
; GNU_SINCOS: callq sincos
; GNU_SINCOS: movsd 16(%rsp), %xmm0
; GNU_SINCOS: addsd 8(%rsp), %xmm0
-; OSX_SINCOS: test2:
+; OSX_SINCOS-LABEL: test2:
; OSX_SINCOS: callq ___sincos_stret
; OSX_SINCOS: addsd %xmm1, %xmm0
define x86_fp80 @test3(x86_fp80 %x) nounwind {
entry:
-; GNU_SINCOS: test3:
+; GNU_SINCOS-LABEL: test3:
; GNU_SINCOS: callq sinl
; GNU_SINCOS: callq cosl
; GNU_SINCOS: ret
declare x86_fp80 @sinl(x86_fp80) readonly
-; SIN: test1:
+; SIN-LABEL: test1:
define float @test1(float %X) {
%Y = call float @sinf(float %X) readonly
ret float %Y
; SAFE: test1
; SAFE-NOT: fsin
-; SIN: test2:
+; SIN-LABEL: test2:
define double @test2(double %X) {
%Y = call double @sin(double %X) readonly
ret double %Y
; SAFE: test2
; SAFE-NOT: fsin
-; SIN: test3:
+; SIN-LABEL: test3:
define x86_fp80 @test3(x86_fp80 %X) {
%Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
ret x86_fp80 %Y
declare x86_fp80 @cosl(x86_fp80) readonly
-; SIN: test4:
-; COS: test3:
+; SIN-LABEL: test4:
+; COS-LABEL: test3:
define float @test4(float %X) {
%Y = call float @cosf(float %X) readonly
ret float %Y
overflow:
%t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
ret i1 false
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: imull
; CHECK-NEXT: jno
}
normal:
%t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
ret i1 true
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: imull
; CHECK-NEXT: jno
}
%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2)
%tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: addl
; CHECK-NEXT: addl
; CHECK-NEXT: ret
%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4)
%tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: addl
; CHECK: mull
; CHECK-NEXT: ret
ret i1 %overflow
; Was returning false, should return true (not constant folded yet though).
; PR13991
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK-NOT: xorb
}
%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
ret <2 x float> %tmp9
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK-NOT: shufps $16
; CHECK: shufps $1,
; CHECK-NOT: shufps $16
define <4 x i32> @test1(<4 x i32> %x, <4 x i32> %y) {
%m = mul <4 x i32> %x, %y
ret <4 x i32> %m
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: pshufd $49
; CHECK: pmuludq
; CHECK: pshufd $49
ret <8 x i16> %shl
}
-; CHECK: test_sllw_1:
+; CHECK-LABEL: test_sllw_1:
; CHECK: psllw $0, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_sllw_2:
+; CHECK-LABEL: test_sllw_2:
; CHECK: paddw %xmm0, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_sllw_3:
+; CHECK-LABEL: test_sllw_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_slld_1:
+; CHECK-LABEL: test_slld_1:
; CHECK: pslld $0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_slld_2:
+; CHECK-LABEL: test_slld_2:
; CHECK: paddd %xmm0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_slld_3:
+; CHECK-LABEL: test_slld_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_sllq_1:
+; CHECK-LABEL: test_sllq_1:
; CHECK: psllq $0, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_sllq_2:
+; CHECK-LABEL: test_sllq_2:
; CHECK: paddq %xmm0, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_sllq_3:
+; CHECK-LABEL: test_sllq_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_sraw_1:
+; CHECK-LABEL: test_sraw_1:
; CHECK: psraw $0, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_sraw_2:
+; CHECK-LABEL: test_sraw_2:
; CHECK: psraw $1, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_sraw_3:
+; CHECK-LABEL: test_sraw_3:
; CHECK: psraw $16, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srad_1:
+; CHECK-LABEL: test_srad_1:
; CHECK: psrad $0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srad_2:
+; CHECK-LABEL: test_srad_2:
; CHECK: psrad $1, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srad_3:
+; CHECK-LABEL: test_srad_3:
; CHECK: psrad $32, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_srlw_1:
+; CHECK-LABEL: test_srlw_1:
; CHECK: psrlw $0, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_srlw_2:
+; CHECK-LABEL: test_srlw_2:
; CHECK: psrlw $1, %xmm0
; CHECK-NEXT: ret
ret <8 x i16> %shl
}
-; CHECK: test_srlw_3:
+; CHECK-LABEL: test_srlw_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srld_1:
+; CHECK-LABEL: test_srld_1:
; CHECK: psrld $0, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srld_2:
+; CHECK-LABEL: test_srld_2:
; CHECK: psrld $1, %xmm0
; CHECK-NEXT: ret
ret <4 x i32> %shl
}
-; CHECK: test_srld_3:
+; CHECK-LABEL: test_srld_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_srlq_1:
+; CHECK-LABEL: test_srlq_1:
; CHECK: psrlq $0, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_srlq_2:
+; CHECK-LABEL: test_srlq_2:
; CHECK: psrlq $1, %xmm0
; CHECK-NEXT: ret
ret <2 x i64> %shl
}
-; CHECK: test_srlq_3:
+; CHECK-LABEL: test_srlq_3:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: ret
store <2 x double> %tmp9, <2 x double>* %r, align 16
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movl 8(%esp), %eax
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movlpd 12(%esp), %xmm0
store <2 x double> %tmp9, <2 x double>* %r, align 16
ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl 8(%esp), %eax
; CHECK-NEXT: movapd (%eax), %xmm0
; CHECK-NEXT: movhpd 12(%esp), %xmm0
}
define <4 x i32> @test5(i8** %ptr) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: pxor
; CHECK: punpcklbw
; CHECK: punpcklwd
store <4 x float> %tmp2, <4 x float>* %res
ret void
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: movaps (%eax), %xmm0
; CHECK: movaps %xmm0, (%eax)
}
store <4 x float> %2, <4 x float>* null
ret void
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: xorps %xmm0, %xmm0
; CHECK: movaps %xmm0, 0
}
%tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3 ; <<4 x i32>> [#uses=1]
%tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp16
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: movups (%eax), %xmm0
}
%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp13
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: movups 8(%esp), %xmm0
}
%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp13
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: movaps 4(%esp), %xmm0
}
%tmp = insertelement <2 x double> undef, double %a, i32 0 ; <<2 x double>> [#uses=1]
%tmp7 = insertelement <2 x double> %tmp, double %b, i32 1 ; <<2 x double>> [#uses=1]
ret <2 x double> %tmp7
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: movaps 4(%esp), %xmm0
}
%tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1]
store <4 x float> %tmp4, <4 x float>* null
ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: movhlps
; CHECK: shufps
}
%tmp21 = fsub <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
%tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp27
-; CHECK: test14:
+; CHECK-LABEL: test14:
; CHECK: subps [[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]]
; CHECK: addps [[X1]], [[X0:%xmm[0-9]+]]
; CHECK: movlhps [[X2]], [[X0]]
%tmp3 = load <4 x float>* %x ; <<4 x float>> [#uses=1]
%tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp4
-; CHECK: test15:
+; CHECK-LABEL: test15:
; CHECK: movhlps %xmm1, %xmm0
}
; PR8900
-; CHECK: test16:
+; CHECK-LABEL: test16:
; CHECK: unpcklpd
; CHECK: ret
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movntss
tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
ret void
declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movntsd
tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
ret void
declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: extrq
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
ret <2 x i64> %1
declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: extrq
%1 = bitcast <2 x i64> %y to <16 x i8>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: insertq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
ret <2 x i64> %1
declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: insertq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
ret <2 x i64> %1
call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x)
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: andl $-16, %esp
; CHECK: movl %esp, %esi
; CHECK-NOT: rep;movsl
%0 = ptrtoint [2048 x i8]* %buffer to i32
%and = and i32 %0, -16
ret i32 %and
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK-NOT: and
; CHECK: ret
}
store i32 %D, i32* %a0, align 4
ret void
-; X64: test1:
+; X64-LABEL: test1:
; X64: movb %sil, (%rdi)
-; X32: test1:
+; X32-LABEL: test1:
; X32: movb 8(%esp), %al
; X32: movb %al, (%{{.*}})
}
%D = or i32 %B, %CS
store i32 %D, i32* %a0, align 4
ret void
-; X64: test2:
+; X64-LABEL: test2:
; X64: movb %sil, 1(%rdi)
-; X32: test2:
+; X32-LABEL: test2:
; X32: movb 8(%esp), %al
; X32: movb %al, 1(%{{.*}})
}
%D = or i32 %B, %C
store i32 %D, i32* %a0, align 4
ret void
-; X64: test3:
+; X64-LABEL: test3:
; X64: movw %si, (%rdi)
-; X32: test3:
+; X32-LABEL: test3:
; X32: movw 8(%esp), %ax
; X32: movw %ax, (%{{.*}})
}
%D = or i32 %B, %CS
store i32 %D, i32* %a0, align 4
ret void
-; X64: test4:
+; X64-LABEL: test4:
; X64: movw %si, 2(%rdi)
-; X32: test4:
+; X32-LABEL: test4:
; X32: movl 8(%esp), %eax
; X32: movw %ax, 2(%{{.*}})
}
%D = or i64 %B, %CS
store i64 %D, i64* %a0, align 4
ret void
-; X64: test5:
+; X64-LABEL: test5:
; X64: movw %si, 2(%rdi)
-; X32: test5:
+; X32-LABEL: test5:
; X32: movzwl 8(%esp), %eax
; X32: movw %ax, 2(%{{.*}})
}
%D = or i64 %B, %CS
store i64 %D, i64* %a0, align 4
ret void
-; X64: test6:
+; X64-LABEL: test6:
; X64: movb %sil, 5(%rdi)
-; X32: test6:
+; X32-LABEL: test6:
; X32: movb 8(%esp), %al
; X32: movb %al, 5(%{{.*}})
}
%D = or i64 %B, %CS
store i64 %D, i64* %a0, align 4
ret i32 %OtherLoad
-; X64: test7:
+; X64-LABEL: test7:
; X64: movb %sil, 5(%rdi)
-; X32: test7:
+; X32-LABEL: test7:
; X32: movb 8(%esp), %cl
; X32: movb %cl, 5(%{{.*}})
}
@g_16 = internal global i32 -1
-; X64: test8:
+; X64-LABEL: test8:
; X64-NEXT: movl _g_16(%rip), %eax
; X64-NEXT: movl $0, _g_16(%rip)
; X64-NEXT: orl $1, %eax
ret void
}
-; X64: test9:
+; X64-LABEL: test9:
; X64-NEXT: orb $1, _g_16(%rip)
; X64-NEXT: ret
define void @test9() nounwind {
}
; rdar://8494845 + PR8244
-; X64: test10:
+; X64-LABEL: test10:
; X64-NEXT: movsbl (%rdi), %eax
; X64-NEXT: shrl $8, %eax
; X64-NEXT: ret
%struct.S2 = type { i64, i16, [2 x i8], i8, [3 x i8], [7 x i8], i8, [8 x i8] }
@s2 = external global %struct.S2, align 16
define void @test2() nounwind uwtable ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: mov
; CHECK-NEXT: and
; CHECK-NEXT: ret
%xor = xor i32 %x, 31
%sub = sub i32 32, %xor
ret i32 %sub
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: xorl $-32
; CHECK-NEXT: addl $33
; CHECK-NEXT: ret
; Don't zero extend the test operands to pointer type if it can be avoided.
; rdar://8781238
define void @test2(i32 %x) nounwind ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: cmpl $6
; CHECK: ja
declare void @bar()
define void @test3(i32 %x) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: cmpl $5
; CHECK: ja
; CHECK: cmpl $4
i32 20, label %if.then5
]
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: unr
; CHECK: cmpl $10
; CHECK: bar
target triple = "i386-unknown-freebsd9.0"
define double @test1(double %x) nounwind readnone {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movl foo@GOT
; CHECK-NEXT: jmpl
%1 = tail call double @foo(double %x) nounwind readnone
declare double @foo(double) readnone
define double @test2(double %x) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: movl sin@GOT
; CHECK-NEXT: jmpl
%1 = tail call double @sin(double %x) nounwind readnone
ret i32 %call
}
-; CALL: test1:
+; CALL-LABEL: test1:
; CALL-NOT: ret
; CALL: callq helper
; CALL: ret
-; JMP: test1:
+; JMP-LABEL: test1:
; JMP-NOT: ret
; JMP: jmp helper # TAILCALL
ret i32 %call
}
-; CALL: test2:
+; CALL-LABEL: test2:
; CALL-NOT: ret
; CALL: callq test2
; CALL: ret
-; JMP: test2:
+; JMP-LABEL: test2:
; JMP-NOT: ret
; JMP: jmp test2 # TAILCALL
target triple = "x86_64-apple-darwin7"
define i32 @test(i32* %P, i32* %G) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: ret
; CHECK: testl (%{{.*}}), %{{.*}}
; CHECK: ret
}
define i32 @test2(i32* %P, i32* %G) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK-NOT: ret
; CHECK: testl (%{{.*}}), %{{.*}}
; CHECK: ret
}
define i32 @test3(i32* %P, i32* %G) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK-NOT: ret
; CHECK: testl (%{{.*}}), %{{.*}}
; CHECK: ret
; rdar://10291355
define i32 @test() nounwind readonly ssp {
entry:
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: movq _a@TLVP(%rip),
; CHECK: callq *
; CHECK: movl (%rax), [[REGISTER:%[a-z]+]]
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
-; CHECK: test0:
+; CHECK-LABEL: test0:
; CHECK: ud2
define i32 @test0() noreturn nounwind {
entry:
unreachable
}
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: int3
define i32 @test1() noreturn nounwind {
entry:
%Y = trunc i32 %X to i1
ret i1 %Y
}
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: andl $1, %eax
define i1 @test2(i32 %val, i32 %mask) nounwind {
ret_false:
ret i1 false
}
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: btl %eax
define i32 @test3(i8* %ptr) nounwind {
cond_false:
ret i32 42
}
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: testb $1, (%eax)
define i32 @test4(i8* %ptr) nounwind {
cond_false:
ret i32 42
}
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: testb $1, 4(%esp)
define i32 @test5(double %d) nounwind {
cond_false:
ret i32 42
}
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: testb $1
@G = external global i32
define i32 @test1(i32 %X) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: mov
; CHECK: leal 1(%rdi)
%Z = add i32 %X, 1
; commutted (which would require inserting a copy).
define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: leal
; CHECK-NOT: leal
; CHECK-NOT: mov
; rdar://9002648
define i64 @test3(i64 %x) nounwind readnone ssp {
entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: leaq (%rdi,%rdi), %rax
; CHECK-NOT: addq
; CHECK-NEXT: ret
%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
%tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: addl
; CHECK-NEXT: addl
; CHECK-NEXT: ret
%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4)
%tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: addl
; CHECK: mull
; CHECK-NEXT: ret
; Use the flags on the add.
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: addl
; CHECK-NOT: test
; CHECK: cmovnsl
; Don't use the flags result of the and here, since the and has no
; other use. A simple test is better.
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: testb $16, {{%dil|%cl}}
define void @test2(i32 %x) nounwind {
; Do use the flags result of the and here, since the and has another use.
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: andl $16, %e
; CHECK-NEXT: jne
store float %c, float* %P2
ret void
-; X64: test1:
+; X64-LABEL: test1:
; X64-NEXT: pshufd $1, %xmm0, %xmm1
; X64-NEXT: addss %xmm0, %xmm1
; X64-NEXT: movss %xmm1, (%rdi)
; X64-NEXT: ret
-; W64: test1:
+; W64-LABEL: test1:
; W64-NEXT: movdqa (%rcx), %xmm0
; W64-NEXT: pshufd $1, %xmm0, %xmm1
; W64-NEXT: addss %xmm0, %xmm1
; W64-NEXT: movss %xmm1, (%rdx)
; W64-NEXT: ret
-; X32: test1:
+; X32-LABEL: test1:
; X32-NEXT: pshufd $1, %xmm0, %xmm1
; X32-NEXT: addss %xmm0, %xmm1
; X32-NEXT: movl 4(%esp), %eax
%Z = fadd <2 x float> %Q, %R
ret <2 x float> %Z
-; X64: test2:
+; X64-LABEL: test2:
; X64-NEXT: addps %xmm1, %xmm0
; X64-NEXT: ret
-; W64: test2:
+; W64-LABEL: test2:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps (%rdx), %xmm0
; W64-NEXT: ret
-; X32: test2:
+; X32-LABEL: test2:
; X32: addps %xmm1, %xmm0
}
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
ret <2 x float> %C
-; X64: test3:
+; X64-LABEL: test3:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
-; W64: test3:
+; W64-LABEL: test3:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
-; X32: test3:
+; X32-LABEL: test3:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
}
define <2 x float> @test4(<2 x float> %A) nounwind {
%C = fadd <2 x float> %A, %A
ret <2 x float> %C
-; X64: test4:
+; X64-LABEL: test4:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
-; W64: test4:
+; W64-LABEL: test4:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
-; X32: test4:
+; X32-LABEL: test4:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
}
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
-; X64: test5:
+; X64-LABEL: test5:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
-; W64: test5:
+; W64-LABEL: test5:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
-; X32: test5:
+; X32-LABEL: test5:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test1:
+; SSE42-LABEL: test1:
; SSE42: pcmpgtq
; SSE42: ret
-; SSE41: test1:
+; SSE41-LABEL: test1:
; SSE41-NOT: pcmpgtq
; SSE41: ret
-; SSE2: test1:
+; SSE2-LABEL: test1:
; SSE2-NOT: pcmpgtq
; SSE2: ret
}
define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test2:
+; SSE42-LABEL: test2:
; SSE42: pcmpeqq
; SSE42: ret
-; SSE41: test2:
+; SSE41-LABEL: test2:
; SSE41: pcmpeqq
; SSE41: ret
-; SSE2: test2:
+; SSE2-LABEL: test2:
; SSE2-NOT: pcmpeqq
; SSE2: ret
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: pcmpgtd
; CHECK: ret
}
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: pcmp
; CHECK: pcmp
; CHECK: pxor
}
define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: pcmpgtd
; CHECK: movdqa
; CHECK: ret
}
define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movdqa
; CHECK: pcmpgtd
; CHECK: ret
}
define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: pcmpeqd
; CHECK: pshufd $-79
; CHECK: pand
}
define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
; CHECK: pcmpeqd
; CHECK: pshufd $-79
; CHECK: pand
; CHECK-NEXT: .long 0
; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 0
-; CHECK: test7:
+; CHECK-LABEL: test7:
; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
; CHECK: pxor [[CONSTREG]]
; CHECK: pxor [[CONSTREG]]
}
define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0
}
define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0
}
define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm1
; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 2147483648
; CHECK-NEXT: .long 2147483648
-; CHECK: test11:
+; CHECK-LABEL: test11:
; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
; CHECK: pxor [[CONSTREG]]
; CHECK: pxor [[CONSTREG]]
}
define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test12:
+; CHECK-LABEL: test12:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0
}
define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test13:
+; CHECK-LABEL: test13:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm0
}
define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test14:
+; CHECK-LABEL: test14:
; CHECK: pxor
; CHECK: pxor
; CHECK: pcmpgtd %xmm1
define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
%y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
ret <4 x i32> %y
-}
\ No newline at end of file
+}
store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P
ret void
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK-NOT: pshufd
; CHECK: punpcklbw
; CHECK: punpcklbw
store <4 x float> %tmp10, <4 x float>* %P
ret void
-; SSE2: test_v4sf:
+; SSE2-LABEL: test_v4sf:
; SSE2: pshufd $0
-; SSE3: test_v4sf:
+; SSE3-LABEL: test_v4sf:
; SSE3: pshufd $0
}
store <2 x double> %tmp6, <2 x double>* %P
ret void
-; SSE2: test_v2sd:
+; SSE2-LABEL: test_v2sd:
; SSE2: shufpd $0
-; SSE3: test_v2sd:
+; SSE3-LABEL: test_v2sd:
; SSE3: movddup
}
%tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
%tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1]
ret i16 %tmp69
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: subss LCPI0_
; CHECK: mulss LCPI0_
; CHECK: minss LCPI0_
%tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
%tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
ret i16 %tmp69
-; CHECK: test2:
+; CHECK-LABEL: test2:
; CHECK: addss LCPI1_
; CHECK: mulss LCPI1_
; CHECK: minss LCPI1_
%B = insertelement <4 x float> undef, float %a, i32 0
%X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)
ret <4 x float> %X
-; CHECK: test3:
+; CHECK-LABEL: test3:
; CHECK: roundss $4, (%eax), %xmm0
}
%q = call <4 x float> @f()
%X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4)
ret <4 x float> %X
-; CHECK: test4:
+; CHECK-LABEL: test4:
; CHECK: movss (%eax), %xmm
; CHECK: call
; CHECK: roundss $4, %xmm{{.*}}, %xmm0
%0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double
4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone
ret <2 x double> %0
-; CHECK: test5:
+; CHECK-LABEL: test5:
; CHECK: mov
; CHECK: mov
; CHECK: cvtsi2sd
; Test that we are not lowering uinttofp to scalars
define <4 x float> @test1(<4 x i32> %A) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: cvtsd2ss
; CHECK: ret
%C = uitofp <4 x i32> %A to <4 x float>
; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; SSE2: test1:
+; SSE2-LABEL: test1:
; SSE2: movdqa
; SSE2: psrad $31
; SSE2-NEXT: padd
; SSE2-NEXT: pxor
; SSE2-NEXT: ret
-; SSSE3: test1:
+; SSSE3-LABEL: test1:
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test1:
+; AVX2-LABEL: test1:
; AVX2: vpabsd
; AVX2-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
}
define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; SSE2: test2:
+; SSE2-LABEL: test2:
; SSE2: movdqa
; SSE2: psrad $31
; SSE2-NEXT: padd
; SSE2-NEXT: pxor
; SSE2-NEXT: ret
-; SSSE3: test2:
+; SSSE3-LABEL: test2:
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test2:
+; AVX2-LABEL: test2:
; AVX2: vpabsd
; AVX2-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
}
define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; SSE2: test3:
+; SSE2-LABEL: test3:
; SSE2: movdqa
; SSE2: psraw $15
; SSE2-NEXT: padd
; SSE2-NEXT: pxor
; SSE2-NEXT: ret
-; SSSE3: test3:
+; SSSE3-LABEL: test3:
; SSSE3: pabsw
; SSSE3-NEXT: ret
-; AVX2: test3:
+; AVX2-LABEL: test3:
; AVX2: vpabsw
; AVX2-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a
}
define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; SSE2: test4:
+; SSE2-LABEL: test4:
; SSE2: pxor
; SSE2: pcmpgtb
; SSE2-NEXT: padd
; SSE2-NEXT: pxor
; SSE2-NEXT: ret
-; SSSE3: test4:
+; SSSE3-LABEL: test4:
; SSSE3: pabsb
; SSSE3-NEXT: ret
-; AVX2: test4:
+; AVX2-LABEL: test4:
; AVX2: vpabsb
; AVX2-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a
}
define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; SSE2: test5:
+; SSE2-LABEL: test5:
; SSE2: movdqa
; SSE2: psrad $31
; SSE2-NEXT: padd
; SSE2-NEXT: pxor
; SSE2-NEXT: ret
-; SSSE3: test5:
+; SSSE3-LABEL: test5:
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test5:
+; AVX2-LABEL: test5:
; AVX2: vpabsd
; AVX2-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
}
define <8 x i32> @test6(<8 x i32> %a) nounwind {
-; SSSE3: test6:
+; SSSE3-LABEL: test6:
; SSSE3: pabsd
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test6:
+; AVX2-LABEL: test6:
; AVX2: vpabsd {{.*}}%ymm
; AVX2-NEXT: ret
%tmp1neg = sub <8 x i32> zeroinitializer, %a
}
define <8 x i32> @test7(<8 x i32> %a) nounwind {
-; SSSE3: test7:
+; SSSE3-LABEL: test7:
; SSSE3: pabsd
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test7:
+; AVX2-LABEL: test7:
; AVX2: vpabsd {{.*}}%ymm
; AVX2-NEXT: ret
%tmp1neg = sub <8 x i32> zeroinitializer, %a
}
define <16 x i16> @test8(<16 x i16> %a) nounwind {
-; SSSE3: test8:
+; SSSE3-LABEL: test8:
; SSSE3: pabsw
; SSSE3: pabsw
; SSSE3-NEXT: ret
-; AVX2: test8:
+; AVX2-LABEL: test8:
; AVX2: vpabsw {{.*}}%ymm
; AVX2-NEXT: ret
%tmp1neg = sub <16 x i16> zeroinitializer, %a
}
define <32 x i8> @test9(<32 x i8> %a) nounwind {
-; SSSE3: test9:
+; SSSE3-LABEL: test9:
; SSSE3: pabsb
; SSSE3: pabsb
; SSSE3-NEXT: ret
-; AVX2: test9:
+; AVX2-LABEL: test9:
; AVX2: vpabsb {{.*}}%ymm
; AVX2-NEXT: ret
%tmp1neg = sub <32 x i8> zeroinitializer, %a
}
define <8 x i32> @test10(<8 x i32> %a) nounwind {
-; SSSE3: test10:
+; SSSE3-LABEL: test10:
; SSSE3: pabsd
; SSSE3: pabsd
; SSSE3-NEXT: ret
-; AVX2: test10:
+; AVX2-LABEL: test10:
; AVX2: vpabsd {{.*}}%ymm
; AVX2-NEXT: ret
%tmp1neg = sub <8 x i32> zeroinitializer, %a
for.end: ; preds = %vector.body
ret void
-; SSE4: test1:
+; SSE4-LABEL: test1:
; SSE4: pminsb
-; AVX1: test1:
+; AVX1-LABEL: test1:
; AVX1: vpminsb
-; AVX2: test1:
+; AVX2-LABEL: test1:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test2:
+; SSE4-LABEL: test2:
; SSE4: pminsb
-; AVX1: test2:
+; AVX1-LABEL: test2:
; AVX1: vpminsb
-; AVX2: test2:
+; AVX2-LABEL: test2:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test3:
+; SSE4-LABEL: test3:
; SSE4: pmaxsb
-; AVX1: test3:
+; AVX1-LABEL: test3:
; AVX1: vpmaxsb
-; AVX2: test3:
+; AVX2-LABEL: test3:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test4:
+; SSE4-LABEL: test4:
; SSE4: pmaxsb
-; AVX1: test4:
+; AVX1-LABEL: test4:
; AVX1: vpmaxsb
-; AVX2: test4:
+; AVX2-LABEL: test4:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test5:
+; SSE2-LABEL: test5:
; SSE2: pminub
-; AVX1: test5:
+; AVX1-LABEL: test5:
; AVX1: vpminub
-; AVX2: test5:
+; AVX2-LABEL: test5:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test6:
+; SSE2-LABEL: test6:
; SSE2: pminub
-; AVX1: test6:
+; AVX1-LABEL: test6:
; AVX1: vpminub
-; AVX2: test6:
+; AVX2-LABEL: test6:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test7:
+; SSE2-LABEL: test7:
; SSE2: pmaxub
-; AVX1: test7:
+; AVX1-LABEL: test7:
; AVX1: vpmaxub
-; AVX2: test7:
+; AVX2-LABEL: test7:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test8:
+; SSE2-LABEL: test8:
; SSE2: pmaxub
-; AVX1: test8:
+; AVX1-LABEL: test8:
; AVX1: vpmaxub
-; AVX2: test8:
+; AVX2-LABEL: test8:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test9:
+; SSE2-LABEL: test9:
; SSE2: pminsw
-; AVX1: test9:
+; AVX1-LABEL: test9:
; AVX1: vpminsw
-; AVX2: test9:
+; AVX2-LABEL: test9:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test10:
+; SSE2-LABEL: test10:
; SSE2: pminsw
-; AVX1: test10:
+; AVX1-LABEL: test10:
; AVX1: vpminsw
-; AVX2: test10:
+; AVX2-LABEL: test10:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test11:
+; SSE2-LABEL: test11:
; SSE2: pmaxsw
-; AVX1: test11:
+; AVX1-LABEL: test11:
; AVX1: vpmaxsw
-; AVX2: test11:
+; AVX2-LABEL: test11:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test12:
+; SSE2-LABEL: test12:
; SSE2: pmaxsw
-; AVX1: test12:
+; AVX1-LABEL: test12:
; AVX1: vpmaxsw
-; AVX2: test12:
+; AVX2-LABEL: test12:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test13:
+; SSE4-LABEL: test13:
; SSE4: pminuw
-; AVX1: test13:
+; AVX1-LABEL: test13:
; AVX1: vpminuw
-; AVX2: test13:
+; AVX2-LABEL: test13:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test14:
+; SSE4-LABEL: test14:
; SSE4: pminuw
-; AVX1: test14:
+; AVX1-LABEL: test14:
; AVX1: vpminuw
-; AVX2: test14:
+; AVX2-LABEL: test14:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test15:
+; SSE4-LABEL: test15:
; SSE4: pmaxuw
-; AVX1: test15:
+; AVX1-LABEL: test15:
; AVX1: vpmaxuw
-; AVX2: test15:
+; AVX2-LABEL: test15:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test16:
+; SSE4-LABEL: test16:
; SSE4: pmaxuw
-; AVX1: test16:
+; AVX1-LABEL: test16:
; AVX1: vpmaxuw
-; AVX2: test16:
+; AVX2-LABEL: test16:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test17:
+; SSE4-LABEL: test17:
; SSE4: pminsd
-; AVX1: test17:
+; AVX1-LABEL: test17:
; AVX1: vpminsd
-; AVX2: test17:
+; AVX2-LABEL: test17:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test18:
+; SSE4-LABEL: test18:
; SSE4: pminsd
-; AVX1: test18:
+; AVX1-LABEL: test18:
; AVX1: vpminsd
-; AVX2: test18:
+; AVX2-LABEL: test18:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test19:
+; SSE4-LABEL: test19:
; SSE4: pmaxsd
-; AVX1: test19:
+; AVX1-LABEL: test19:
; AVX1: vpmaxsd
-; AVX2: test19:
+; AVX2-LABEL: test19:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test20:
+; SSE4-LABEL: test20:
; SSE4: pmaxsd
-; AVX1: test20:
+; AVX1-LABEL: test20:
; AVX1: vpmaxsd
-; AVX2: test20:
+; AVX2-LABEL: test20:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test21:
+; SSE4-LABEL: test21:
; SSE4: pminud
-; AVX1: test21:
+; AVX1-LABEL: test21:
; AVX1: vpminud
-; AVX2: test21:
+; AVX2-LABEL: test21:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test22:
+; SSE4-LABEL: test22:
; SSE4: pminud
-; AVX1: test22:
+; AVX1-LABEL: test22:
; AVX1: vpminud
-; AVX2: test22:
+; AVX2-LABEL: test22:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test23:
+; SSE4-LABEL: test23:
; SSE4: pmaxud
-; AVX1: test23:
+; AVX1-LABEL: test23:
; AVX1: vpmaxud
-; AVX2: test23:
+; AVX2-LABEL: test23:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test24:
+; SSE4-LABEL: test24:
; SSE4: pmaxud
-; AVX1: test24:
+; AVX1-LABEL: test24:
; AVX1: vpmaxud
-; AVX2: test24:
+; AVX2-LABEL: test24:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test25:
+; AVX2-LABEL: test25:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test26:
+; AVX2-LABEL: test26:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test27:
+; AVX2-LABEL: test27:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test28:
+; AVX2-LABEL: test28:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test29:
+; AVX2-LABEL: test29:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test30:
+; AVX2-LABEL: test30:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test31:
+; AVX2-LABEL: test31:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test32:
+; AVX2-LABEL: test32:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test33:
+; AVX2-LABEL: test33:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test34:
+; AVX2-LABEL: test34:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test35:
+; AVX2-LABEL: test35:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test36:
+; AVX2-LABEL: test36:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test37:
+; AVX2-LABEL: test37:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test38:
+; AVX2-LABEL: test38:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test39:
+; AVX2-LABEL: test39:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test40:
+; AVX2-LABEL: test40:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test41:
+; AVX2-LABEL: test41:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test42:
+; AVX2-LABEL: test42:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test43:
+; AVX2-LABEL: test43:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test44:
+; AVX2-LABEL: test44:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test45:
+; AVX2-LABEL: test45:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test46:
+; AVX2-LABEL: test46:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test47:
+; AVX2-LABEL: test47:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test48:
+; AVX2-LABEL: test48:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test49:
+; SSE4-LABEL: test49:
; SSE4: pmaxsb
-; AVX1: test49:
+; AVX1-LABEL: test49:
; AVX1: vpmaxsb
-; AVX2: test49:
+; AVX2-LABEL: test49:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test50:
+; SSE4-LABEL: test50:
; SSE4: pmaxsb
-; AVX1: test50:
+; AVX1-LABEL: test50:
; AVX1: vpmaxsb
-; AVX2: test50:
+; AVX2-LABEL: test50:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test51:
+; SSE4-LABEL: test51:
; SSE4: pminsb
-; AVX1: test51:
+; AVX1-LABEL: test51:
; AVX1: vpminsb
-; AVX2: test51:
+; AVX2-LABEL: test51:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test52:
+; SSE4-LABEL: test52:
; SSE4: pminsb
-; AVX1: test52:
+; AVX1-LABEL: test52:
; AVX1: vpminsb
-; AVX2: test52:
+; AVX2-LABEL: test52:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test53:
+; SSE2-LABEL: test53:
; SSE2: pmaxub
-; AVX1: test53:
+; AVX1-LABEL: test53:
; AVX1: vpmaxub
-; AVX2: test53:
+; AVX2-LABEL: test53:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test54:
+; SSE2-LABEL: test54:
; SSE2: pmaxub
-; AVX1: test54:
+; AVX1-LABEL: test54:
; AVX1: vpmaxub
-; AVX2: test54:
+; AVX2-LABEL: test54:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test55:
+; SSE2-LABEL: test55:
; SSE2: pminub
-; AVX1: test55:
+; AVX1-LABEL: test55:
; AVX1: vpminub
-; AVX2: test55:
+; AVX2-LABEL: test55:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test56:
+; SSE2-LABEL: test56:
; SSE2: pminub
-; AVX1: test56:
+; AVX1-LABEL: test56:
; AVX1: vpminub
-; AVX2: test56:
+; AVX2-LABEL: test56:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test57:
+; SSE2-LABEL: test57:
; SSE2: pmaxsw
-; AVX1: test57:
+; AVX1-LABEL: test57:
; AVX1: vpmaxsw
-; AVX2: test57:
+; AVX2-LABEL: test57:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test58:
+; SSE2-LABEL: test58:
; SSE2: pmaxsw
-; AVX1: test58:
+; AVX1-LABEL: test58:
; AVX1: vpmaxsw
-; AVX2: test58:
+; AVX2-LABEL: test58:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test59:
+; SSE2-LABEL: test59:
; SSE2: pminsw
-; AVX1: test59:
+; AVX1-LABEL: test59:
; AVX1: vpminsw
-; AVX2: test59:
+; AVX2-LABEL: test59:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; SSE2: test60:
+; SSE2-LABEL: test60:
; SSE2: pminsw
-; AVX1: test60:
+; AVX1-LABEL: test60:
; AVX1: vpminsw
-; AVX2: test60:
+; AVX2-LABEL: test60:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test61:
+; SSE4-LABEL: test61:
; SSE4: pmaxuw
-; AVX1: test61:
+; AVX1-LABEL: test61:
; AVX1: vpmaxuw
-; AVX2: test61:
+; AVX2-LABEL: test61:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test62:
+; SSE4-LABEL: test62:
; SSE4: pmaxuw
-; AVX1: test62:
+; AVX1-LABEL: test62:
; AVX1: vpmaxuw
-; AVX2: test62:
+; AVX2-LABEL: test62:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test63:
+; SSE4-LABEL: test63:
; SSE4: pminuw
-; AVX1: test63:
+; AVX1-LABEL: test63:
; AVX1: vpminuw
-; AVX2: test63:
+; AVX2-LABEL: test63:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test64:
+; SSE4-LABEL: test64:
; SSE4: pminuw
-; AVX1: test64:
+; AVX1-LABEL: test64:
; AVX1: vpminuw
-; AVX2: test64:
+; AVX2-LABEL: test64:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test65:
+; SSE4-LABEL: test65:
; SSE4: pmaxsd
-; AVX1: test65:
+; AVX1-LABEL: test65:
; AVX1: vpmaxsd
-; AVX2: test65:
+; AVX2-LABEL: test65:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test66:
+; SSE4-LABEL: test66:
; SSE4: pmaxsd
-; AVX1: test66:
+; AVX1-LABEL: test66:
; AVX1: vpmaxsd
-; AVX2: test66:
+; AVX2-LABEL: test66:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test67:
+; SSE4-LABEL: test67:
; SSE4: pminsd
-; AVX1: test67:
+; AVX1-LABEL: test67:
; AVX1: vpminsd
-; AVX2: test67:
+; AVX2-LABEL: test67:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test68:
+; SSE4-LABEL: test68:
; SSE4: pminsd
-; AVX1: test68:
+; AVX1-LABEL: test68:
; AVX1: vpminsd
-; AVX2: test68:
+; AVX2-LABEL: test68:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test69:
+; SSE4-LABEL: test69:
; SSE4: pmaxud
-; AVX1: test69:
+; AVX1-LABEL: test69:
; AVX1: vpmaxud
-; AVX2: test69:
+; AVX2-LABEL: test69:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test70:
+; SSE4-LABEL: test70:
; SSE4: pmaxud
-; AVX1: test70:
+; AVX1-LABEL: test70:
; AVX1: vpmaxud
-; AVX2: test70:
+; AVX2-LABEL: test70:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test71:
+; SSE4-LABEL: test71:
; SSE4: pminud
-; AVX1: test71:
+; AVX1-LABEL: test71:
; AVX1: vpminud
-; AVX2: test71:
+; AVX2-LABEL: test71:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; SSE4: test72:
+; SSE4-LABEL: test72:
; SSE4: pminud
-; AVX1: test72:
+; AVX1-LABEL: test72:
; AVX1: vpminud
-; AVX2: test72:
+; AVX2-LABEL: test72:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test73:
+; AVX2-LABEL: test73:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test74:
+; AVX2-LABEL: test74:
; AVX2: vpmaxsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test75:
+; AVX2-LABEL: test75:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test76:
+; AVX2-LABEL: test76:
; AVX2: vpminsb
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test77:
+; AVX2-LABEL: test77:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test78:
+; AVX2-LABEL: test78:
; AVX2: vpmaxub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test79:
+; AVX2-LABEL: test79:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test80:
+; AVX2-LABEL: test80:
; AVX2: vpminub
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test81:
+; AVX2-LABEL: test81:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test82:
+; AVX2-LABEL: test82:
; AVX2: vpmaxsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test83:
+; AVX2-LABEL: test83:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test84:
+; AVX2-LABEL: test84:
; AVX2: vpminsw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test85:
+; AVX2-LABEL: test85:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test86:
+; AVX2-LABEL: test86:
; AVX2: vpmaxuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test87:
+; AVX2-LABEL: test87:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test88:
+; AVX2-LABEL: test88:
; AVX2: vpminuw
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test89:
+; AVX2-LABEL: test89:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test90:
+; AVX2-LABEL: test90:
; AVX2: vpmaxsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test91:
+; AVX2-LABEL: test91:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test92:
+; AVX2-LABEL: test92:
; AVX2: vpminsd
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test93:
+; AVX2-LABEL: test93:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test94:
+; AVX2-LABEL: test94:
; AVX2: vpmaxud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test95:
+; AVX2-LABEL: test95:
; AVX2: vpminud
}
for.end: ; preds = %vector.body
ret void
-; AVX2: test96:
+; AVX2-LABEL: test96:
; AVX2: vpminud
}
target triple = "x86_64-apple-darwin8"
; This should be a single mov, not a load of immediate + andq.
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: movl %edi, %eax
define i64 @test(i64 %x) nounwind {
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubb:
+; CHECK-LABEL: test_psubb:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubw:
+; CHECK-LABEL: test_psubw:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubd:
+; CHECK-LABEL: test_psubd:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubsb:
+; CHECK-LABEL: test_psubsb:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubswv:
+; CHECK-LABEL: test_psubswv:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubusbv:
+; CHECK-LABEL: test_psubusbv:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
ret i64 %retval.0.extract.i15
}
-; CHECK: test_psubuswv:
+; CHECK-LABEL: test_psubuswv:
; CHECK: callq getFirstParam
; CHECK: callq getSecondParam
; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
%tmp = xor <4 x i32> undef, undef
ret <4 x i32> %tmp
-; X32: test1:
+; X32-LABEL: test1:
; X32: xorps %xmm0, %xmm0
; X32: ret
}
define i32 @test2() nounwind{
%tmp = xor i32 undef, undef
ret i32 %tmp
-; X32: test2:
+; X32-LABEL: test2:
; X32: xorl %eax, %eax
; X32: ret
}
%tmp4 = lshr i32 %tmp3, 1
ret i32 %tmp4
-; X64: test3:
+; X64-LABEL: test3:
; X64: notl
; X64: andl
; X64: shrl
; X64: ret
-; X32: test3:
+; X32-LABEL: test3:
; X32: movl 8(%esp), %eax
; X32: notl %eax
; X32: andl 4(%esp), %eax
bb12:
ret i32 %tmp3
-; X64: test4:
+; X64-LABEL: test4:
; X64: notl [[REG:%[a-z]+]]
; X64: andl {{.*}}[[REG]]
-; X32: test4:
+; X32-LABEL: test4:
; X32: notl [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG]]
}
br i1 %tmp10, label %bb12, label %bb
bb12:
ret i16 %tmp3
-; X64: test5:
+; X64-LABEL: test5:
; X64: notl [[REG:%[a-z]+]]
; X64: andl {{.*}}[[REG]]
-; X32: test5:
+; X32-LABEL: test5:
; X32: notl [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG]]
}
br i1 %tmp10, label %bb12, label %bb
bb12:
ret i8 %tmp3
-; X64: test6:
+; X64-LABEL: test6:
; X64: notb [[REG:%[a-z]+]]
; X64: andb {{.*}}[[REG]]
-; X32: test6:
+; X32-LABEL: test6:
; X32: notb [[REG:%[a-z]+]]
; X32: andb {{.*}}[[REG]]
}
br i1 %tmp10, label %bb12, label %bb
bb12:
ret i32 %tmp3
-; X64: test7:
+; X64-LABEL: test7:
; X64: xorl $2147483646, [[REG:%[a-z]+]]
; X64: andl {{.*}}[[REG]]
-; X32: test7:
+; X32-LABEL: test7:
; X32: xorl $2147483646, [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG]]
}
%t1 = sub i32 0, %a
%t2 = add i32 %t1, -1
ret i32 %t2
-; X64: test8:
+; X64-LABEL: test8:
; X64: notl {{%eax|%edi|%ecx}}
-; X32: test8:
+; X32-LABEL: test8:
; X32: notl %eax
}
%1 = and i32 %a, 4096
%2 = xor i32 %1, 4096
ret i32 %2
-; X64: test9:
+; X64-LABEL: test9:
; X64: notl [[REG:%[a-z]+]]
; X64: andl {{.*}}[[REG:%[a-z]+]]
-; X32: test9:
+; X32-LABEL: test9:
; X32: notl [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG:%[a-z]+]]
}
%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
ret <4 x i32> %2
-; X64: test10:
+; X64-LABEL: test10:
; X64: andnps
-; X32: test10:
+; X32-LABEL: test10:
; X32: andnps
}
; RUN: llc < %s -march=xcore | FileCheck %s
define i1 @test(double %F) nounwind {
entry:
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: xor
%0 = fsub double -0.000000e+00, %F
%1 = fcmp olt double 0.000000e+00, %0
declare i32 @llvm.xcore.getid()
define i32 @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: get r11, id
; CHECK-NEXT: mov r0, r11
%result = call i32 @llvm.xcore.getid()
}
define i32 @testct(i8 addrspace(1)* %r) {
-; CHECK: testct:
+; CHECK-LABEL: testct:
; CHECK: testct r0, res[r0]
%result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define i32 @testwct(i8 addrspace(1)* %r) {
-; CHECK: testwct:
+; CHECK-LABEL: testwct:
; CHECK: testwct r0, res[r0]
%result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
ret i32 %result
; RUN: llc < %s -march=xcore | FileCheck %s
define i32 @test() noreturn nounwind {
entry:
-; CHECK: test:
+; CHECK-LABEL: test:
; CHECK: ldc
; CHECK: ecallf
tail call void @llvm.trap( )
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