call void @sideeffect1()
ret void
}
+
+; The liveout instruction can be located after the branch condition.
+define void @one_pred_with_extra_op_externally_used_only_after_cond_distant_phi(i8 %v0, i8 %v1, i8 %v3, i8 %v4, i8 %v5) {
+; CHECK-LABEL: @one_pred_with_extra_op_externally_used_only_after_cond_distant_phi(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
+; CHECK-NEXT: br i1 [[C0]], label [[PRED:%.*]], label [[LEFT_END:%.*]]
+; CHECK: pred:
+; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
+; CHECK-NEXT: br i1 [[C1]], label [[DISPATCH:%.*]], label [[FINAL_RIGHT:%.*]]
+; CHECK: dispatch:
+; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
+; CHECK-NEXT: [[V2_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
+; CHECK-NEXT: br i1 [[C3]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT]]
+; CHECK: final_left:
+; CHECK-NEXT: call void @sideeffect0()
+; CHECK-NEXT: call void @use8(i8 [[V2_ADJ]])
+; CHECK-NEXT: br label [[LEFT_END]]
+; CHECK: left_end:
+; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: call void @sideeffect1()
+; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
+; CHECK-NEXT: ret void
+; CHECK: final_right:
+; CHECK-NEXT: call void @sideeffect2()
+; CHECK-NEXT: ret void
+;
+entry:
+ %c0 = icmp eq i8 %v0, 0
+ br i1 %c0, label %pred, label %left_end
+pred:
+ %c1 = icmp eq i8 %v1, 0
+ br i1 %c1, label %dispatch, label %final_right
+dispatch:
+ %c3 = icmp eq i8 %v3, 0
+ %v2_adj = add i8 %v4, %v5
+ br i1 %c3, label %final_left, label %final_right
+final_left:
+ call void @sideeffect0()
+ call void @use8(i8 %v2_adj)
+ br label %left_end
+left_end:
+ %merge_left = phi i8 [ %v2_adj, %final_left ], [ 0, %entry ]
+ call void @sideeffect1()
+ call void @use8(i8 %merge_left)
+ ret void
+final_right:
+ call void @sideeffect2()
+ ret void
+}
+define void @two_preds_with_extra_op_externally_used_only_after_cond(i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8 %v4, i8 %v5) {
+; CHECK-LABEL: @two_preds_with_extra_op_externally_used_only_after_cond(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
+; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
+; CHECK: pred0:
+; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
+; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
+; CHECK: pred1:
+; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
+; CHECK-NEXT: br i1 [[C2]], label [[DISPATCH]], label [[FINAL_RIGHT:%.*]]
+; CHECK: dispatch:
+; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
+; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
+; CHECK-NEXT: br i1 [[C3]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
+; CHECK: final_left:
+; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ]], [[DISPATCH]] ], [ 0, [[PRED0]] ]
+; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
+; CHECK-NEXT: call void @sideeffect0()
+; CHECK-NEXT: ret void
+; CHECK: final_right:
+; CHECK-NEXT: call void @sideeffect1()
+; CHECK-NEXT: ret void
+;
+entry:
+ %c0 = icmp eq i8 %v0, 0
+ br i1 %c0, label %pred0, label %pred1
+pred0:
+ %c1 = icmp eq i8 %v1, 0
+ br i1 %c1, label %final_left, label %dispatch
+pred1:
+ %c2 = icmp eq i8 %v2, 0
+ br i1 %c2, label %dispatch, label %final_right
+dispatch:
+ %c3 = icmp eq i8 %v3, 0
+ %v3_adj = add i8 %v4, %v5
+ br i1 %c3, label %final_left, label %final_right
+final_left:
+ %merge_left = phi i8 [ %v3_adj, %dispatch ], [ 0, %pred0 ]
+ call void @use8(i8 %merge_left)
+ call void @sideeffect0()
+ ret void
+final_right:
+ call void @sideeffect1()
+ ret void
+}