X86: Fix alias info in GenInlinedIndexOf().

For 32-bit X86, GenInlinedIndexOf() pushes and pops EDI. In
one branch it then calls Load32Disp() with adjusted stack
offset. That calculates wrong alias_info for the generated
insn. If left unfixed, this could confuse load hoisting.

Bug: 17128502

(cherry picked from commit 74de63bb1cc275b411cae28a96f9b3a78b939bc2)

Change-Id: I5dc82b7aae9e9655e75843a952b8ebb04269f46b

diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 2498298..75279d7 100755 (executable)
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -1337,10 +1337,12 @@ bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) {
       if (!cu_->target64 && rl_start.location != kLocPhysReg) {
         // Load the start index from stack, remembering that we pushed EDI.
         int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t);
-        {
-          ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
-          Load32Disp(rs_rX86_SP, displacement, rs_rDI);
-        }
+        ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
+        Load32Disp(rs_rX86_SP, displacement, rs_rDI);
+        // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it.
+        DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info));
+        int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - 1;
+        AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false);
       } else {
         LoadValueDirectFixed(rl_start, rs_rDI);
       }