drm/i915/tc: Fix system hang on ADL-P during TypeC PHY disconnect

The PHY ownership release->AUX PW disable steps during a modeset
disable->PHY disconnect sequence can hang the system if the PHY
disconnect happens after disabling the PHY's PLL. The spec doesn't
require a specific order for these two steps, so this issue is still
being root caused by HW/FW teams. Until that is found, let's make
sure the disconnect happens before the PLL is disabled, and do this on
all platforms for consistency.

v2: Add a TODO comment to remove the w/a once the issue is root
    caused/fixed. (Jose)

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-7-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 4a14db6..40faa18 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -834,6 +834,14 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port)
        intel_tc_port_lock(dig_port);
        --dig_port->tc_link_refcount;
        intel_tc_port_unlock(dig_port);
+
+       /*
+        * Disconnecting the PHY after the PHY's PLL gets disabled may
+        * hang the system on ADL-P, so disconnect the PHY here synchronously.
+        * TODO: remove this once the root cause of the ordering requirement
+        * is found/fixed.
+        */
+       intel_tc_port_flush_work(dig_port);
 }
 
 static bool