OSDN Git Service

drm/nv50-/disp: allow dumping core channel state at first supervisor intr
authorBen Skeggs <bskeggs@redhat.com>
Thu, 20 Feb 2014 13:19:58 +0000 (23:19 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 26 Mar 2014 04:00:38 +0000 (14:00 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

index 3b70868..e94866e 100644 (file)
@@ -1520,12 +1520,14 @@ nv50_disp_intr_supervisor(struct work_struct *work)
 {
        struct nv50_disp_priv *priv =
                container_of(work, struct nv50_disp_priv, supervisor);
+       struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
        u32 super = nv_rd32(priv, 0x610030);
        int head;
 
        nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super);
 
        if (priv->super & 0x00000010) {
+               nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core);
                for (head = 0; head < priv->head.nr; head++) {
                        if (!(super & (0x00000020 << head)))
                                continue;
index 8d553dc..0eac17b 100644 (file)
@@ -1174,6 +1174,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 {
        struct nv50_disp_priv *priv =
                container_of(work, struct nv50_disp_priv, supervisor);
+       struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
        u32 mask[4];
        int head;
 
@@ -1184,6 +1185,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
        }
 
        if (priv->super & 0x00000001) {
+               nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core);
                for (head = 0; head < priv->head.nr; head++) {
                        if (!(mask[head] & 0x00001000))
                                continue;