// setcc patterns
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
Instruction SLTuOp, Register ZEROReg> {
+ def : MipsPat<(seteq RC:$lhs, 0),
+ (SLTiuOp RC:$lhs, 1)>;
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),
--- /dev/null
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+; CHECK: seteq0:
+; CHECK: sltiu ${{[0-9]+}}, $4, 1
+
+define i32 @seteq0(i32 %a) {
+entry:
+ %cmp = icmp eq i32 %a, 0
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}