drm/i915: Move broxton vswing sequence to intel_dpio_phy.c

The vswing sequence is related to the DPIO phy, so move it closer to the
rest of DPIO phy related code.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/59aa5c85a115c5cbed81e793f20cd7b9f8de694b.1475770848.git-series.ander.conselvan.de.oliveira@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c642f10..7e79298 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3761,6 +3761,9 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+                                 enum port port, u32 margin, u32 scale,
+                                 u32 enable, u32 deemphasis);
 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 51ca8ea..938ac4d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1547,7 +1547,6 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 {
        const struct bxt_ddi_buf_trans *ddi_translations;
        u32 n_entries, i;
-       uint32_t val;
 
        if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
                n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
@@ -1576,38 +1575,11 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
                }
        }
 
-       /*
-        * While we write to the group register to program all lanes at once we
-        * can read only lane registers and we pick lanes 0/1 for that.
-        */
-       val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-       val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
-       I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
-
-       val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
-       val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
-       val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
-              ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
-       I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
-
-       val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-       val &= ~SCALE_DCOMP_METHOD;
-       if (ddi_translations[level].enable)
-               val |= SCALE_DCOMP_METHOD;
-
-       if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
-               DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
-
-       I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
-
-       val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-       val &= ~DE_EMPHASIS;
-       val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
-       I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
-
-       val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-       val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
-       I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+       bxt_ddi_phy_set_signal_level(dev_priv, port,
+                                    ddi_translations[level].margin,
+                                    ddi_translations[level].scale,
+                                    ddi_translations[level].enable,
+                                    ddi_translations[level].deemphasis);
 }
 
 static uint32_t translate_signal_level(int signal_levels)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 6806296..2a18724 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -114,6 +114,45 @@
  *     -----------------
  */
 
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+                                 enum port port, u32 margin, u32 scale,
+                                 u32 enable, u32 deemphasis)
+{
+       u32 val;
+
+       /*
+        * While we write to the group register to program all lanes at once we
+        * can read only lane registers and we pick lanes 0/1 for that.
+        */
+       val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+       val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
+       I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+
+       val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
+       val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
+       val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
+       I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
+
+       val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
+       val &= ~SCALE_DCOMP_METHOD;
+       if (enable)
+               val |= SCALE_DCOMP_METHOD;
+
+       if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
+               DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
+
+       I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
+
+       val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
+       val &= ~DE_EMPHASIS;
+       val |= deemphasis << DEEMPH_SHIFT;
+       I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
+
+       val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+       val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
+       I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+}
+
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
                            enum dpio_phy phy)
 {