[InstCombine] add vector tests for icmp sgt smin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281623 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/min-positive.ll b/test/Transforms/InstCombine/min-positive.ll
index 82d1799..58258e1 100644 (file)
--- a/test/Transforms/InstCombine/min-positive.ll
+++ b/test/Transforms/InstCombine/min-positive.ll
@@ -3,8 +3,8 @@
 
 @g = external global i32
 
-define i1 @test(i32 %other) {
-; CHECK-LABEL: @test(
+define i1 @smin(i32 %other) {
+; CHECK-LABEL: @smin(
 ; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt i32 %other, 0
 ; CHECK-NEXT:    ret i1 [[TEST]]
 ;
@@ -15,8 +15,27 @@ define i1 @test(i32 %other) {
   ret i1 %test
 }
 
-define i1 @test2(i32 %other) {
-; CHECK-LABEL: @test2(
+; Range metadata doesn't work for vectors, so find another way to trigger isKnownPositive().
+
+define <2 x i1> @smin_vec(<2 x i32> %x, <2 x i32> %other) {
+; CHECK-LABEL: @smin_vec(
+; CHECK-NEXT:    [[NOTNEG:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
+; CHECK-NEXT:    [[POSITIVE:%.*]] = or <2 x i32> [[NOTNEG]], <i32 1, i32 1>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[POSITIVE]], %other
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[POSITIVE]], <2 x i32> %other
+; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[TEST]]
+;
+  %notneg = and <2 x i32> %x, <i32 7, i32 7>
+  %positive = or <2 x i32> %notneg, <i32 1, i32 1>
+  %cmp = icmp slt <2 x i32> %positive, %other
+  %sel = select <2 x i1> %cmp, <2 x i32> %positive, <2 x i32> %other
+  %test = icmp sgt <2 x i32> %sel, zeroinitializer
+  ret <2 x i1> %test
+}
+
+define i1 @smin_commute(i32 %other) {
+; CHECK-LABEL: @smin_commute(
 ; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt i32 %other, 0
 ; CHECK-NEXT:    ret i1 [[TEST]]
 ;
@@ -27,9 +46,27 @@ define i1 @test2(i32 %other) {
   ret i1 %test
 }
 
+define <2 x i1> @smin_commute_vec(<2 x i32> %x, <2 x i32> %other) {
+; CHECK-LABEL: @smin_commute_vec(
+; CHECK-NEXT:    [[NOTNEG:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
+; CHECK-NEXT:    [[POSITIVE:%.*]] = or <2 x i32> [[NOTNEG]], <i32 1, i32 1>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[POSITIVE]], %other
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> %other, <2 x i32> [[POSITIVE]]
+; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[TEST]]
+;
+  %notneg = and <2 x i32> %x, <i32 7, i32 7>
+  %positive = or <2 x i32> %notneg, <i32 1, i32 1>
+  %cmp = icmp slt <2 x i32> %positive, %other
+  %sel = select <2 x i1> %cmp, <2 x i32> %other, <2 x i32> %positive
+  %test = icmp sgt <2 x i32> %sel, zeroinitializer
+  ret <2 x i1> %test
+}
+
 ; %positive might be zero
-define i1 @test3(i32 %other) {
-; CHECK-LABEL: @test3(
+
+define i1 @maybe_not_positive(i32 %other) {
+; CHECK-LABEL: @maybe_not_positive(
 ; CHECK-NEXT:    [[POSITIVE:%.*]] = load i32, i32* @g, align 4, !range !0
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[POSITIVE]], %other
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[POSITIVE]], i32 %other
@@ -42,3 +79,19 @@ define i1 @test3(i32 %other) {
   %test = icmp sgt i32 %sel, 0
   ret i1 %test
 }
+
+define <2 x i1> @maybe_not_positive_vec(<2 x i32> %x, <2 x i32> %other) {
+; CHECK-LABEL: @maybe_not_positive_vec(
+; CHECK-NEXT:    [[NOTNEG:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[NOTNEG]], %other
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[NOTNEG]], <2 x i32> %other
+; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt <2 x i32> [[SEL]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[TEST]]
+;
+  %notneg = and <2 x i32> %x, <i32 7, i32 7>
+  %cmp = icmp slt <2 x i32> %notneg, %other
+  %sel = select <2 x i1> %cmp, <2 x i32> %notneg, <2 x i32> %other
+  %test = icmp sgt <2 x i32> %sel, zeroinitializer
+  ret <2 x i1> %test
+}
+