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drm/amd/display: Populate DP2.0 output type for DML pipe
authorGeorge Shen <george.shen@amd.com>
Fri, 15 Apr 2022 01:29:38 +0000 (21:29 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 9 Nov 2022 22:41:41 +0000 (17:41 -0500)
[Why]
DCN3.2 DML logic uses a new output type for DP2.0,
which will enable validation to pass for higher BW
timings that require DP2.0 link rates.

[How]
Populate the DML pipe with DP2.0 output type if
the signal type of the pipe_ctx is 128b/132b.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

index 602e885..75dbb7e 100644 (file)
@@ -1296,6 +1296,8 @@ int dcn20_populate_dml_pipes_from_context(
                case SIGNAL_TYPE_DISPLAY_PORT_MST:
                case SIGNAL_TYPE_DISPLAY_PORT:
                        pipes[pipe_cnt].dout.output_type = dm_dp;
+                       if (is_dp_128b_132b_signal(&res_ctx->pipe_ctx[i]))
+                               pipes[pipe_cnt].dout.output_type = dm_dp2p0;
                        break;
                case SIGNAL_TYPE_EDP:
                        pipes[pipe_cnt].dout.output_type = dm_edp;