radeonsi: don't invoke DCC decompression in update_all_texture_descriptors

This fixes a bug uncovered by the 17-part patch series, specifically:
  "gallium/radeon: merge dirty_fb_counter and dirty_tex_descriptor_counter"

If dirty_tex_counter has been updated and set_shader_image invokes DCC
decompression, the DCC decompression itself checks the counter and updates
descriptors, which in turn invokes the same DCC decompression. The blitter
can't handle the recursion and the driver eventually crashes.

Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit a0740d59aa97a08d89998cb57138e8217a331af6)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 4a9fcd0..e8177c2 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -660,7 +660,8 @@ si_mark_image_range_valid(const struct pipe_image_view *view)
 
 static void si_set_shader_image(struct si_context *ctx,
                                unsigned shader,
-                               unsigned slot, const struct pipe_image_view *view)
+                               unsigned slot, const struct pipe_image_view *view,
+                               bool skip_decompress)
 {
        struct si_screen *screen = ctx->screen;
        struct si_images_info *images = &ctx->images[shader];
@@ -702,7 +703,7 @@ static void si_set_shader_image(struct si_context *ctx,
                assert(!tex->is_depth);
                assert(tex->fmask.size == 0);
 
-               if (uses_dcc &&
+               if (uses_dcc && !skip_decompress &&
                    (view->access & PIPE_IMAGE_ACCESS_WRITE ||
                     !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
                        /* If DCC can't be disabled, at least decompress it.
@@ -776,10 +777,10 @@ si_set_shader_images(struct pipe_context *pipe,
 
        if (views) {
                for (i = 0, slot = start_slot; i < count; ++i, ++slot)
-                       si_set_shader_image(ctx, shader, slot, &views[i]);
+                       si_set_shader_image(ctx, shader, slot, &views[i], false);
        } else {
                for (i = 0, slot = start_slot; i < count; ++i, ++slot)
-                       si_set_shader_image(ctx, shader, slot, NULL);
+                       si_set_shader_image(ctx, shader, slot, NULL, false);
        }
 
        si_update_compressed_tex_shader_mask(ctx, shader);
@@ -1710,7 +1711,7 @@ void si_update_all_texture_descriptors(struct si_context *sctx)
                            view->resource->target == PIPE_BUFFER)
                                continue;
 
-                       si_set_shader_image(sctx, shader, i, view);
+                       si_set_shader_image(sctx, shader, i, view, true);
                }
 
                /* Sampler views. */