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power: qpnp-fg-gen3: add support to configure batt_therm coefficients
authorcyizhao <cyizhao@codeaurora.org>
Tue, 24 Jan 2017 09:08:55 +0000 (17:08 +0800)
committercyizhao <cyizhao@codeaurora.org>
Tue, 14 Feb 2017 02:13:14 +0000 (10:13 +0800)
Add support to configure battery thermal coefficients so that different
battery thermistors can be supported. These coefficients can be
configured via "qcom,battery-thermal-coefficients" device tree property.

CRs-Fixed: 2004461
Change-Id: Iff25acd397a68c31057dff4db1896d46e396adc6
Signed-off-by: Yingwei Zhao <cyizhao@codeaurora.org>
Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt
drivers/power/supply/qcom/fg-core.h
drivers/power/supply/qcom/qpnp-fg-gen3.c

index dffacc7..af80de7 100644 (file)
@@ -215,6 +215,12 @@ First Level Node - FG Gen3 device
                    capacity learning cycle. If this is not specified, then
                    the default value is 0. Unit is in decipercentage.
 
+- qcom,battery-thermal-coefficients
+       Usage:      optional
+       Value type: <u8>
+       Definition: Byte array of battery thermal coefficients.
+                   This should be exactly 3 bytes in length.
+
 - qcom,fg-jeita-hyst-temp
        Usage:      optional
        Value type: <u32>
@@ -377,6 +383,7 @@ pmi8998_fg: qpnp,fg {
        qcom,ki-coeff-hi-dischg = <1200 1500 2100>;
        qcom,slope-limit-temp-threshold = <100>;
        qcom,slope-limit-coeffs = <10 11 12 13>;
+       qcom,battery-thermal-coefficients = [9d 50 ff];
        status = "okay";
 
        qcom,fg-batt-soc@4000 {
index 936a3a0..c146654 100644 (file)
@@ -73,6 +73,8 @@
 
 #define SLOPE_LIMIT_COEFF_MAX          31
 
+#define BATT_THERM_NUM_COEFFS          3
+
 /* Debug flag definitions */
 enum fg_debug_flag {
        FG_IRQ                  = BIT(0), /* Show interrupts */
@@ -251,6 +253,7 @@ struct fg_dt_props {
        int     ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS];
        int     ki_coeff_hi_dischg[KI_COEFF_SOC_LEVELS];
        int     slope_limit_coeffs[SLOPE_LIMIT_NUM_COEFFS];
+       u8      batt_therm_coeffs[BATT_THERM_NUM_COEFFS];
 };
 
 /* parameters from battery profile */
index 4dd5edb..5491bcc 100644 (file)
@@ -3035,6 +3035,21 @@ static int fg_hw_init(struct fg_chip *chip)
                }
        }
 
+       /*
+        * configure battery thermal coefficients c1,c2,c3
+        * if its value is not zero.
+        */
+       if (chip->dt.batt_therm_coeffs[0] > 0) {
+               rc = fg_write(chip, BATT_INFO_THERM_C1(chip),
+                       chip->dt.batt_therm_coeffs, BATT_THERM_NUM_COEFFS);
+               if (rc < 0) {
+                       pr_err("Error in writing battery thermal coefficients, rc=%d\n",
+                               rc);
+                       return rc;
+               }
+       }
+
+
        if (chip->dt.recharge_soc_thr > 0 && chip->dt.recharge_soc_thr < 100) {
                rc = fg_set_recharge_soc(chip, chip->dt.recharge_soc_thr);
                if (rc < 0) {
@@ -3807,6 +3822,18 @@ static int fg_parse_dt(struct fg_chip *chip)
                                rc);
        }
 
+       if (of_property_count_elems_of_size(node,
+               "qcom,battery-thermal-coefficients",
+               sizeof(u8)) == BATT_THERM_NUM_COEFFS) {
+               rc = of_property_read_u8_array(node,
+                               "qcom,battery-thermal-coefficients",
+                               chip->dt.batt_therm_coeffs,
+                               BATT_THERM_NUM_COEFFS);
+               if (rc < 0)
+                       pr_warn("Error reading battery thermal coefficients, rc:%d\n",
+                               rc);
+       }
+
        rc = of_property_read_u32(node, "qcom,fg-esr-timer-charging", &temp);
        if (rc < 0)
                chip->dt.esr_timer_charging = -EINVAL;