+
declare spi_controler{
input send_data[8];
output resv_data[8];
+ output MOSI;
+ input MISO;
+ output SS;
+ output SCLK;
func_in send();
- func_in read_MOSI();
- func_in write_MOSO(send_data);
+ func_in read_MISO();
+ func_in write_MOSI(send_data);
}
+
module spi_controler{
reg output_data[8];
reg input_data[8];
- reg work_flg;
+ reg work_flg = 0;
+ reg SS_reg = 1, SCLK_reg = 0,MOSI_reg,MISO_reg;
+
+ func send() seq{
+ {work_flg = 1;SS_reg=0;MOSI_reg:=output_data[7];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[7];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[6];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[5];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[4];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[3];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[2];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[1];}
+ {SCLK_reg=1;}
+ {SCLK_reg=0;MOSI_reg:=output_data[0];}
+
+
+ }
+
+ func read_MISO(){
+ resv_data = input_data;
+ }
+
+ func write_MOSI(send_data){
+ if(work_flg==0){
+ output_data := send_data;
+ }
+ }
+
}