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ARM: dts: imx: Add missing OPP properties for CPUs
authorViresh Kumar <viresh.kumar@linaro.org>
Fri, 25 May 2018 10:32:01 +0000 (16:02 +0530)
committerShawn Guo <shawnguo@kernel.org>
Tue, 3 Jul 2018 12:33:46 +0000 (20:33 +0800)
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.

Add such missing properties.

Fix other missing properties (like clocks, supply, clock latency) as
well to make it all work.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q-cm-fx6.dts
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx7d.dtsi

index a1acd4d..f0607eb 100644 (file)
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               996000  1250000
+                               792000  1175000
+                               396000  1150000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               996000  1175000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
        };
 
index 65ef4ca..18ae4f3 100644 (file)
        >;
 };
 
+&cpu1 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
+&cpu2 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
+&cpu3 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
 &ecspi1 {
        cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
        pinctrl-names = "default";
index 894401c..bbe6561 100644 (file)
                        soc-supply = <&reg_soc>;
                };
 
-               cpu@1 {
+               cpu1: cpu@1 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
 
-               cpu@2 {
+               cpu2: cpu@2 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <2>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
 
-               cpu@3 {
+               cpu3: cpu@3 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <3>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
        };
 
index 7cbc2ff..9a772fc 100644 (file)
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <1>;
+                       operating-points = <
+                               /* KHz  uV */
+                               996000  1075000
+                               792000  975000
+                       >;
                        clock-frequency = <996000000>;
                        operating-points-v2 = <&cpu0_opp_table>;
                };