+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_scalar_add_big
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_UNMERGE_VALUES
- ; CHECK-DAG: [[CARRY0_32:%.*]](s32) = G_CONSTANT i32 0
- ; CHECK-DAG: [[CARRY0:%[0-9]+]](s1) = G_TRUNC [[CARRY0_32]]
- ; CHECK: [[RES_LO:%.*]](s64), [[CARRY:%.*]](s1) = G_UADDE %0, %2, [[CARRY0]]
- ; CHECK: [[RES_HI:%.*]](s64), {{%.*}}(s1) = G_UADDE %1, %3, [[CARRY]]
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_UNMERGE_VALUES
- ; CHECK: %x0 = COPY [[RES_LO]]
- ; CHECK: %x1 = COPY [[RES_HI]]
+ ; CHECK-LABEL: name: test_scalar_add_big
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY %x2
+ ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY %x3
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
+ ; CHECK: [[UADDE:%[0-9]+]](s64), [[UADDE1:%[0-9]+]](s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
+ ; CHECK: [[UADDE2:%[0-9]+]](s64), [[UADDE3:%[0-9]+]](s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+ ; CHECK: %x0 = COPY [[UADDE]](s64)
+ ; CHECK: %x1 = COPY [[UADDE2]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s64) = COPY %x2
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_scalar_add_small
- ; CHECK: [[A:%.*]](s64) = COPY %x0
- ; CHECK: [[B:%.*]](s64) = COPY %x1
- ; CHECK: [[OP0:%.*]](s32) = G_TRUNC [[A]]
- ; CHECK: [[OP1:%.*]](s32) = G_TRUNC [[B]]
- ; CHECK: [[RES32:%.*]](s32) = G_ADD [[OP0]], [[OP1]]
- ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
+ ; CHECK-LABEL: name: test_scalar_add_small
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[ADD]](s32)
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+ ; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
body: |
bb.0.entry:
liveins: %q0, %q1, %q2, %q3
- ; CHECK-LABEL: name: test_vector_add
- ; CHECK-NOT: G_EXTRACT
- ; CHECK-NOT: G_SEQUENCE
- ; CHECK: [[RES_LO:%.*]](<2 x s64>) = G_ADD %0, %2
- ; CHECK: [[RES_HI:%.*]](<2 x s64>) = G_ADD %1, %3
- ; CHECK-NOT: G_EXTRACT
- ; CHECK-NOT: G_SEQUENCE
- ; CHECK: %q0 = COPY [[RES_LO]]
- ; CHECK: %q1 = COPY [[RES_HI]]
+ ; CHECK-LABEL: name: test_vector_add
+ ; CHECK: [[COPY:%[0-9]+]](<2 x s64>) = COPY %q0
+ ; CHECK: [[COPY1:%[0-9]+]](<2 x s64>) = COPY %q1
+ ; CHECK: [[COPY2:%[0-9]+]](<2 x s64>) = COPY %q2
+ ; CHECK: [[COPY3:%[0-9]+]](<2 x s64>) = COPY %q3
+ ; CHECK: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
+ ; CHECK: [[ADD1:%[0-9]+]](<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
+ ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
+ ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
%0(<2 x s64>) = COPY %q0
%1(<2 x s64>) = COPY %q1
%2(<2 x s64>) = COPY %q2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_scalar_and_small
- ; CHECK: [[A:%.*]](s64) = COPY %x0
- ; CHECK: [[B:%.*]](s64) = COPY %x1
- ; CHECK: [[OP0:%.*]](s32) = G_TRUNC [[A]]
- ; CHECK: [[OP1:%.*]](s32) = G_TRUNC [[B]]
- ; CHECK: [[RES32:%.*]](s32) = G_AND [[OP0]], [[OP1]]
- ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
+ ; CHECK-LABEL: name: test_scalar_and_small
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC2:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[TRUNC1]], [[TRUNC2]]
+ ; CHECK: [[TRUNC3:%[0-9]+]](s8) = G_TRUNC [[AND]](s32)
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
bb.0:
liveins: %w0
+ ; Here the types don't match.
+ ; CHECK-LABEL: name: test_combines_2
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
+ ; CHECK: [[EXTRACT:%[0-9]+]](s1) = G_EXTRACT [[MV]](s64), 0
+ ; CHECK: [[EXTRACT1:%[0-9]+]](s64) = G_EXTRACT [[MV]](s64), 0
%0:_(s32) = COPY %w0
- ; Similarly, here the types don't match.
- ; CHECK-LABEL: name: test_combines_2
- ; CHECK: %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
- ; CHECK: %3(s1) = G_EXTRACT %2(s64), 0
- ; CHECK: %4(s64) = G_EXTRACT %2(s64), 0
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s1) = G_EXTRACT %2, 0
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_combines_3
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
%0:_(s32) = COPY %w0
- ; CHECK-LABEL: name: test_combines_3
- ; CHECK: %1(s32) = G_ADD %0, %0
- ; CHECK-NOT: G_SEQUENCE
- ; CHECK-NOT: G_EXTRACT
- ; CHECK: %5(s32) = G_ADD %0, %1
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
bb.0:
liveins: %x0
+ ; CHECK-LABEL: name: test_combines_4
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY [[COPY]](s64)
+ ; CHECK: [[ADD:%[0-9]+]](s64) = G_ADD [[COPY1]], [[COPY1]]
%0:_(s64) = COPY %x0
- ; CHECK-LABEL: name: test_combines_4
- ; CHECK: %2(s64) = COPY %0(s64)
- ; CHECK: %3(s64) = G_ADD %2, %2
%1:_(s128) = G_MERGE_VALUES %0, %0
%2:_(s64) = G_EXTRACT %1, 0
%3:_(s64) = G_ADD %2, %2
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_combines_5
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
%0:_(s32) = COPY %w0
- ; CHECK-LABEL: name: test_combines_5
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_EXTRACT
- ; CHECK: %5(s32) = G_ADD %0, %1
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
bb.0:
liveins: %w0
+ ; Check that we replace all the uses of a G_EXTRACT.
; CHECK-LABEL: name: test_combines_6
- ; CHECK: %0(s32) = COPY %w0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]]
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[MUL]]
%0:_(s32) = COPY %w0
- ; Check that we replace all the uses of a G_EXTRACT.
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_EXTRACT
- ; CHECK: %3(s32) = G_MUL %0, %0
- ; CHECK: %4(s32) = G_ADD %0, %3
%1:_(s32) = G_MERGE_VALUES %0
%2:_(s32) = G_UNMERGE_VALUES %1
%3:_(s32) = G_MUL %2, %2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
- { id: 5, class: _ }
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_constant
- ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 0
- ; CHECK: %0(s1) = G_TRUNC [[TMP]]
- ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 42
- ; CHECK: %1(s8) = G_TRUNC [[TMP]]
- ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 -1
- ; CHECK: %2(s16) = G_TRUNC [[TMP]]
- ; CHECK: %3(s32) = G_CONSTANT i32 -1
- ; CHECK: %4(s64) = G_CONSTANT i64 1
- ; CHECK: %5(s64) = G_CONSTANT i64 0
+ ; CHECK-LABEL: name: test_constant
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
+ ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 42
+ ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[C1]](s32)
+ ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 -1
+ ; CHECK: [[TRUNC2:%[0-9]+]](s16) = G_TRUNC [[C2]](s32)
+ ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 -1
+ ; CHECK: [[C4:%[0-9]+]](s64) = G_CONSTANT i64 1
+ ; CHECK: [[C5:%[0-9]+]](s64) = G_CONSTANT i64 0
%0(s1) = G_CONSTANT i1 0
%1(s8) = G_CONSTANT i8 42
%2(s16) = G_CONSTANT i16 65535
- { id: 2, class: _ }
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_fconstant
- ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00
- ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
- ; CHECK: %2(s16) = G_FPTRUNC [[TMP]]
+ ; CHECK-LABEL: name: test_fconstant
+ ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK: [[C1:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK: [[C2:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
+ ; CHECK: [[FPTRUNC:%[0-9]+]](s16) = G_FPTRUNC [[C2]](s32)
%0(s32) = G_FCONSTANT float 1.0
%1(s64) = G_FCONSTANT double 2.0
%2(s16) = G_FCONSTANT half 0.0
- { id: 0, class: _ }
body: |
bb.0:
- ; CHECK-LABEL: name: test_global
- ; CHECK: %0(p0) = G_GLOBAL_VALUE @var
+ ; CHECK-LABEL: name: test_global
+ ; CHECK: [[GV:%[0-9]+]](p0) = G_GLOBAL_VALUE @var
%0(p0) = G_GLOBAL_VALUE @var
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
; value stored is forwarded directly from first load.
; CHECK-LABEL: name: test_extracts_1
- ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
- ; CHECK: {{%[0-9]+}}(s64) = G_LOAD
- ; CHECK: [[VAL:%[0-9]+]](s64) = COPY [[LO]]
- ; CHECK: G_STORE [[VAL]]
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
+ ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
+ ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+ ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
+ ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
+ ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
+ ; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
; Low extraction wipes takes whole low register. High extraction is real.
; CHECK-LABEL: name: test_extracts_2
- ; CHECK: [[LO_TMP:%[0-9]+]](s64) = G_LOAD
- ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
- ; CHECK: [[LO:%[0-9]+]](s64) = COPY [[LO_TMP]]
- ; CHECK: [[NEWHI_TMP:%[0-9]+]](s32) = G_EXTRACT [[HI]](s64), 0
- ; CHECK: [[NEWHI:%[0-9]+]](s32) = COPY [[NEWHI_TMP]]
- ; CHECK: G_STORE [[LO]]
- ; CHECK: G_STORE [[NEWHI]]
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
+ ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
+ ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+ ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
+ ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
+ ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[LOAD1]](s64), 0
+ ; CHECK: [[COPY4:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
+ ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
+ ; CHECK: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store 4)
+ ; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
%2:_(p0) = COPY %x2
; CHECK-LABEL: name: test_extracts_3
- ; CHECK: [[LO:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
- ; CHECK: [[HI:%[0-9]+]](s32) = G_EXTRACT %1(s64), 0
- ; CHECK: %3(s64) = G_MERGE_VALUES [[LO]](s32), [[HI]](s32)
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
+ ; CHECK: [[EXTRACT1:%[0-9]+]](s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+ ; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s128) = G_MERGE_VALUES %0, %1
; CHECK-LABEL: name: test_extracts_4
- ; CHECK: [[LO_TMP:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
- ; CHECK: %3(s32) = COPY [[LO_TMP]]
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
+ ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
+ ; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s128) = G_MERGE_VALUES %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
bb.1:
liveins: %s0
; CHECK-LABEL: name: test_fneg_f32
- ; CHECK: [[VAR:%[0-9]+]](s32) = COPY %s0
- ; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
- ; CHECK: [[RES:%[0-9]+]](s32) = G_FSUB [[ZERO]], [[VAR]]
- ; CHECK: %s0 = COPY [[RES]](s32)
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
+ ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[C]], [[COPY]]
+ ; CHECK: %s0 = COPY [[FSUB]](s32)
%0(s32) = COPY %s0
%1(s32) = G_FNEG %0
%s0 = COPY %1(s32)
bb.1:
liveins: %d0
; CHECK-LABEL: name: test_fneg_f64
- ; CHECK: [[VAR:%[0-9]+]](s64) = COPY %d0
- ; CHECK: [[ZERO:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
- ; CHECK: [[RES:%[0-9]+]](s64) = G_FSUB [[ZERO]], [[VAR]]
- ; CHECK: %d0 = COPY [[RES]](s64)
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0
+ ; CHECK: [[C:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
+ ; CHECK: [[FSUB:%[0-9]+]](s64) = G_FSUB [[C]], [[COPY]]
+ ; CHECK: %d0 = COPY [[FSUB]](s64)
%0(s64) = COPY %d0
%1(s64) = G_FNEG %0
%d0 = COPY %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptosi_s32_s32
- ; CHECK: %1(s32) = G_FPTOSI %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s32) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptoui_s32_s32
- ; CHECK: %1(s32) = G_FPTOUI %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s32) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptosi_s32_s64
- ; CHECK: %1(s32) = G_FPTOSI %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s32) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptoui_s32_s64
- ; CHECK: %1(s32) = G_FPTOUI %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s32) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptosi_s64_s32
- ; CHECK: %1(s64) = G_FPTOSI %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s64) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptoui_s64_s32
- ; CHECK: %1(s64) = G_FPTOUI %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s64) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptosi_s64_s64
- ; CHECK: %1(s64) = G_FPTOSI %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s64) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptoui_s64_s64
- ; CHECK: %1(s64) = G_FPTOUI %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s64) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptosi_s1_s32
- ; CHECK: %2(s32) = G_FPTOSI %0
- ; CHECK: %1(s1) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOSI]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s1) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptoui_s1_s32
- ; CHECK: %2(s32) = G_FPTOUI %0
- ; CHECK: %1(s1) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOUI]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s1) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptosi_s8_s64
- ; CHECK: %2(s32) = G_FPTOSI %0
- ; CHECK: %1(s8) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOSI]](s32)
+ %0:_(s64) = COPY %x0
%1:_(s8) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_fptoui_s8_s64
- ; CHECK: %2(s32) = G_FPTOUI %0
- ; CHECK: %1(s8) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOUI]](s32)
+ %0:_(s64) = COPY %x0
%1:_(s8) = G_FPTOUI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptosi_s16_s32
- ; CHECK: %2(s32) = G_FPTOSI %0
- ; CHECK: %1(s16) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOSI]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s16) = G_FPTOSI %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_fptoui_s16_s32
- ; CHECK: %2(s32) = G_FPTOUI %0
- ; CHECK: %1(s16) = G_TRUNC %2
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOUI]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s16) = G_FPTOUI %0
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_gep_small
- ; CHECK: [[A:%.*]](p0) = COPY %x0
- ; CHECK: [[B:%.*]](s64) = COPY %x1
- ; CHECK: [[C:%.*]](s64) = G_CONSTANT i64 56
- ; CHECK: [[SRC:%.*]](s64) = COPY [[B]](s64)
- ; CHECK: [[SHL:%.*]](s64) = G_SHL [[SRC]], [[C]]
- ; CHECK: [[SEXT:%.*]](s64) = G_ASHR [[SHL]], [[C]]
- ; CHECK: G_GEP [[A]], [[SEXT]]
-
+ ; CHECK-LABEL: name: test_gep_small
+ ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
+ ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 56
+ ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY [[COPY1]](s64)
+ ; CHECK: [[SHL:%[0-9]+]](s64) = G_SHL [[COPY2]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]](s64) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY]], [[ASHR]](s64)
+ ; CHECK: %x0 = COPY [[GEP]](p0)
%0(p0) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %x0
- ; CHECK-LABEL: name: test_copy
- ; CHECK: %0(s64) = COPY %x0
- ; CHECK-NEXT: %x0 = COPY %0
+ ; CHECK-LABEL: name: test_copy
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: %x0 = COPY [[COPY]](s64)
%0(s64) = COPY %x0
%x0 = COPY %0
...
name: test_targetspecific
body: |
bb.0:
+
; CHECK-LABEL: name: test_targetspecific
; CHECK: RET_ReallyLR
-
RET_ReallyLR
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_sitofp_s32_s32
- ; CHECK: %1(s32) = G_SITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s32) = G_SITOFP %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_uitofp_s32_s32
- ; CHECK: %1(s32) = G_UITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s32) = G_UITOFP %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_sitofp_s32_s64
- ; CHECK: %1(s32) = G_SITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s32) = G_SITOFP %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_uitofp_s32_s64
- ; CHECK: %1(s32) = G_UITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s32) = G_UITOFP %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_sitofp_s64_s32
- ; CHECK: %1(s64) = G_SITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s64) = G_SITOFP %0
...
body: |
bb.0:
liveins: %w0
- %0:_(s32) = COPY %w0
-
; CHECK-LABEL: name: test_uitofp_s64_s32
- ; CHECK: %1(s64) = G_UITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s32)
+ %0:_(s32) = COPY %w0
%1:_(s64) = G_UITOFP %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_sitofp_s64_s64
- ; CHECK: %1(s64) = G_SITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s64) = G_SITOFP %0
...
body: |
bb.0:
liveins: %x0
- %0:_(s64) = COPY %x0
-
; CHECK-LABEL: name: test_uitofp_s64_s64
- ; CHECK: %1(s64) = G_UITOFP %0
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+ ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s64)
+ %0:_(s64) = COPY %x0
%1:_(s64) = G_UITOFP %0
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_sitofp_s32_s1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 31
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%1:_(s1) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_sitofp_s32_s1
- ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 31
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
- ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: %2(s32) = G_SITOFP [[SEXT]]
%2:_(s32) = G_SITOFP %1
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_uitofp_s32_s1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 1
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%1:_(s1) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_uitofp_s32_s1
- ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 1
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
- ; CHECK: [[RES:%.*]](s32) = G_UITOFP [[ZEXT]]
%2:_(s32) = G_UITOFP %1
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_sitofp_s64_s8
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 24
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%1:_(s8) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_sitofp_s64_s8
- ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
- ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: %2(s64) = G_SITOFP [[SEXT]]
%2:_(s64) = G_SITOFP %1
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_uitofp_s64_s8
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 255
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%1:_(s8) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_uitofp_s64_s8
- ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 255
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
- ; CHECK: %2(s64) = G_UITOFP [[ZEXT]]
%2:_(s64) = G_UITOFP %1
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_sitofp_s32_s16
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 16
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
%0:_(s32) = COPY %w0
%1:_(s16) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_sitofp_s32_s16
- ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 16
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
- ; CHECK: [[SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: %2(s32) = G_SITOFP [[SEXT]]
%2:_(s32) = G_SITOFP %1
...
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_uitofp_s32_s16
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
%0:_(s32) = COPY %w0
%1:_(s16) = G_TRUNC %0
-
- ; CHECK-LABEL: name: test_uitofp_s32_s16
- ; CHECK: [[C:%.*]](s32) = G_CONSTANT i32 65535
- ; CHECK: [[SRC:%.*]](s32) = COPY %0(s32)
- ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C]]
- ; CHECK: [[RES:%.*]](s32) = G_UITOFP [[ZEXT]]
%2:_(s32) = G_UITOFP %1
...
; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
; CHECK: [[MUL:%[0-9]+]](s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: [[SMULH:%[0-9]+]](s64) = G_SMULH [[COPY]], [[COPY1]]
- ; CHECK: [[C2:%[0-9]+]](s64) = G_CONSTANT i64 0
- ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C2]]
+ ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 0
+ ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
-
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
bb.0:
liveins: %w0, %w1, %w2
; CHECK-LABEL: name: test_legalize_merge_v3s32
- ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
- ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1
- ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2
- ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32)
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
+ ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY %w2
+ ; CHECK: [[MV:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
%0(s32) = COPY %w0
%1(s32) = COPY %w1
%2(s32) = COPY %w2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
bb.0.entry:
liveins:
; CHECK-LABEL: name: test_implicit_def
- ; CHECK: [[LO:%[0-9]+]](s64) = G_IMPLICIT_DEF
- ; CHECK: [[HI:%[0-9]+]](s64) = G_IMPLICIT_DEF
- ; CHECK: %0(s128) = G_MERGE_VALUES [[LO]](s64), [[HI]](s64)
+ ; CHECK: [[DEF:%[0-9]+]](s64) = G_IMPLICIT_DEF
+ ; CHECK: [[DEF1:%[0-9]+]](s64) = G_IMPLICIT_DEF
+ ; CHECK: [[MV:%[0-9]+]](s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
%0:_(s128) = G_IMPLICIT_DEF
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s
# We run the legalizer to combine the trivial EXTRACT_SEQ pair, leaving %1 and
define void @unused_reg() { ret void }
---
-# CHECK-LABEL: name: unused_reg
name: unused_reg
legalized: true
regBankSelected: true
tracksRegLiveness: true
-# CHECK: body:
-# CHECK: %0 = COPY %w0
-# CHECK: %w0 = COPY %0
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: unused_reg
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
+ ; CHECK: %w0 = COPY [[COPY]]
%0:gpr(s32) = COPY %w0
%1:gpr(s32) = G_MERGE_VALUES %0(s32)
%2:gpr(s32) = G_UNMERGE_VALUES %1(s32)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
...
---
-# CHECK-LABEL: name: const_s32
name: const_s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
-# CHECK: body:
-# CHECK: %0 = MOVi32imm 42
body: |
bb.0:
+ ; CHECK-LABEL: name: const_s32
+ ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 42
+ ; CHECK: %w0 = COPY [[MOVi32imm]]
%0(s32) = G_CONSTANT i32 42
%w0 = COPY %0(s32)
...
---
-# CHECK-LABEL: name: const_s64
name: const_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
-# CHECK: body:
-# CHECK: %0 = MOVi64imm 1234567890123
body: |
bb.0:
+ ; CHECK-LABEL: name: const_s64
+ ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234567890123
+ ; CHECK: %x0 = COPY [[MOVi64imm]]
%0(s64) = G_CONSTANT i64 1234567890123
%x0 = COPY %0(s64)
...
---
-# CHECK-LABEL: name: fconst_s32
name: fconst_s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi32imm 1080033280
-# CHECK: %0 = COPY [[TMP]]
body: |
bb.0:
+ ; CHECK-LABEL: name: fconst_s32
+ ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1080033280
+ ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi32imm]]
+ ; CHECK: %s0 = COPY [[COPY]]
%0(s32) = G_FCONSTANT float 3.5
%s0 = COPY %0(s32)
...
---
-# CHECK-LABEL: name: fconst_s64
name: fconst_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi64imm 4607182418800017408
-# CHECK: %0 = COPY [[TMP]]
body: |
bb.0:
+ ; CHECK-LABEL: name: fconst_s64
+ ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 4607182418800017408
+ ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi64imm]]
+ ; CHECK: %d0 = COPY [[COPY]]
%0(s64) = G_FCONSTANT double 1.0
%d0 = COPY %0(s64)
...
---
-# CHECK-LABEL: name: fconst_s32_0
name: fconst_s32_0
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = FMOVS0
-# CHECK: %s0 = COPY [[TMP]]
body: |
bb.0:
+ ; CHECK-LABEL: name: fconst_s32_0
+ ; CHECK: [[FMOVS0_:%[0-9]+]] = FMOVS0
+ ; CHECK: %s0 = COPY [[FMOVS0_]]
%0(s32) = G_FCONSTANT float 0.0
%s0 = COPY %0(s32)
...
---
-# CHECK-LABEL: name: fconst_s64_0
name: fconst_s64_0
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
-# CHECK: body:
-# CHECK: [[TMP:%[0-9]+]] = FMOVD0
-# CHECK: %s0 = COPY [[TMP]]
body: |
bb.0:
+ ; CHECK-LABEL: name: fconst_s64_0
+ ; CHECK: [[FMOVD0_:%[0-9]+]] = FMOVD0
+ ; CHECK: %s0 = COPY [[FMOVD0_]]
%0(s64) = G_FCONSTANT double 0.0
%s0 = COPY %0(s64)
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm64-- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
--- |
...
---
-# CHECK-LABEL: name: test_dbg_value
name: test_dbg_value
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: %w0
+ ; CHECK-LABEL: name: test_dbg_value
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
+ ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[COPY]], [[COPY]]
+ ; CHECK: %w0 = COPY [[ADDWrr]]
+ ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY %w0
%1:gpr(s32) = G_ADD %0, %0
%w0 = COPY %1(s32)
-
- ; CHECK: %0 = COPY %w0
- ; CHECK-NEXT: %1 = ADDWrr %0, %0
- ; CHECK-NEXT: %w0 = COPY %1
- ; CHECK-NEXT: DBG_VALUE debug-use %1, debug-use _, !7, !DIExpression(), debug-location !9
-
DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9
...
---
-# CHECK-LABEL: name: test_dbg_value_dead
name: test_dbg_value_dead
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: %w0
- %0:gpr(s32) = COPY %w0
-
+ ; CHECK-LABEL: name: test_dbg_value_dead
; CHECK-NOT: COPY
; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9
-
+ %0:gpr(s32) = COPY %w0
DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
entry:
ret i32 0
}
-
+
declare i32 @printf(i8*, ...)
...
---
-# CHECK-LABEL: name: main
name: main
alignment: 2
exposesReturnsTwice: false
regBankSelected: true
selected: false
tracksRegLiveness: true
-registers:
+registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 13, class: gpr }
- { id: 14, class: gpr }
- { id: 15, class: gpr }
-frameInfo:
+frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
-# CHECK: body:
-# CHECK: %1 = COPY %w0
-# CHECK-NOT: %2 = ORNWrr %wzr, %1
-# CHECK: %4 = EONWrr %1, %3
body: |
bb.1.entry:
liveins: %w0
+ ; CHECK-LABEL: name: main
+ ; CHECK: liveins: %w0
+ ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
+ ; CHECK: [[EONWrr:%[0-9]+]] = EONWrr [[COPY]], [[MOVi32imm]]
+ ; CHECK: %w0 = COPY [[EONWrr]]
%0(s32) = G_CONSTANT i32 -1
%3(s32) = G_CONSTANT i32 1
%1(s32) = COPY %w0
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0, %vgpr1
- ; CHECK-LABEL: name: test_add
- ; CHECK: %2(s32) = G_ADD %0, %1
+ ; CHECK-LABEL: name: test_add
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
+ ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY1]]
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_ADD %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0, %vgpr1
- ; CHECK-LABEL: name: test_and
- ; CHECK: %2(s32) = G_AND %0, %1
+ ; CHECK-LABEL: name: test_and
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY]], [[COPY1]]
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_AND %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0
- ; CHECK-LABEL: name: test_bitcast
- ; CHECK: %1(<2 x s16>) = G_BITCAST %0
- ; CHECK: %2(s32) = G_BITCAST %1
+ ; CHECK-LABEL: name: test_bitcast
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[BITCAST:%[0-9]+]](<2 x s16>) = G_BITCAST [[COPY]](s32)
+ ; CHECK: [[BITCAST1:%[0-9]+]](s32) = G_BITCAST [[BITCAST]](<2 x s16>)
%0(s32) = COPY %vgpr0
%1(<2 x s16>) = G_BITCAST %0
%2(s32) = G_BITCAST %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
- { id: 1, class: _ }
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_constant
- ; CHECK: %0(s32) = G_CONSTANT i32 5
- ; CHECK: %1(s1) = G_CONSTANT i1 false
+ ; CHECK-LABEL: name: test_constant
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 5
+ ; CHECK: [[C1:%[0-9]+]](s1) = G_CONSTANT i1 false
%0(s32) = G_CONSTANT i32 5
%1(s1) = G_CONSTANT i1 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
- { id: 1, class: _ }
body: |
bb.0.entry:
- ; CHECK-LABEL: name: test_fconstant
- ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
- ; CHECK: %1(s32) = G_FCONSTANT float 7.5
+ ; CHECK-LABEL: name: test_fconstant
+ ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK: [[C1:%[0-9]+]](s32) = G_FCONSTANT float 7.500000e+00
%0(s32) = G_FCONSTANT float 1.0
%1(s32) = G_FCONSTANT float 7.5
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0, %vgpr1
- ; CHECK-LABEL: name: test_fmul
- ; CHECK: %2(s32) = G_FMUL %0, %1
+ ; CHECK-LABEL: name: test_fmul
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
+ ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY1]]
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_FMUL %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0.entry:
liveins: %vgpr0
+ ; CHECK-LABEL: name: test_icmp
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
%0(s32) = G_CONSTANT i32 0
%1(s32) = COPY %vgpr0
-
- ; CHECK: %2(s1) = G_ICMP intpred(ne), %0(s32), %1
%2(s1) = G_ICMP intpred(ne), %0, %1
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0, %vgpr1
- ; CHECK-LABEL: name: test_or
- ; CHECK: %2(s32) = G_OR %0, %1
+ ; CHECK-LABEL: name: test_or
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
+ ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[COPY]], [[COPY1]]
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_OR %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
body: |
bb.0:
liveins: %vgpr0
+ ; CHECK-LABEL: name: test_select
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
+ ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
+ ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
+ ; CHECK: [[SELECT:%[0-9]+]](s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
%0(s32) = G_CONSTANT i32 0
%1(s32) = COPY %vgpr0
%2(s1) = G_ICMP intpred(ne), %0, %1
%3(s32) = G_CONSTANT i32 1
%4(s32) = G_CONSTANT i32 2
- ; CHECK: %5(s32) = G_SELECT %2(s1), %3, %4
%5(s32) = G_SELECT %2, %3, %4
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
body: |
bb.0.entry:
liveins: %vgpr0, %vgpr1
- ; CHECK-LABEL: name: test_shl
- ; CHECK: %2(s32) = G_SHL %0, %1
+ ; CHECK-LABEL: name: test_shl
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
+ ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY]], [[COPY1]]
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_SHL %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_icmp_eq_s32() { ret void }
...
---
name: test_icmp_eq_s32
-# CHECK-LABEL: name: test_icmp_eq_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_eq_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ne_s32
-# CHECK-LABEL: name: test_icmp_ne_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_ne_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ugt_s32
-# CHECK-LABEL: name: test_icmp_ugt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_ugt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_uge_s32
-# CHECK-LABEL: name: test_icmp_uge_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_uge_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 2, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ult_s32
-# CHECK-LABEL: name: test_icmp_ult_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_ult_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 3, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_ule_s32
-# CHECK-LABEL: name: test_icmp_ule_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_ule_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sgt_s32
-# CHECK-LABEL: name: test_icmp_sgt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_sgt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sge_s32
-# CHECK-LABEL: name: test_icmp_sge_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_sge_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_slt_s32
-# CHECK-LABEL: name: test_icmp_slt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_slt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_icmp_sle_s32
-# CHECK-LABEL: name: test_icmp_sle_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
bb.0:
liveins: %r0, %r1
+ ; CHECK-LABEL: name: test_icmp_sle_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
%1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_true_s32
-# CHECK-LABEL: name: test_fcmp_true_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_true_s32
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
%1(s32) = COPY %s1
-
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
- ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_false_s32
-# CHECK-LABEL: name: test_fcmp_false_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_false_s32
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
%1(s32) = COPY %s1
-
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
- ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_oeq_s32
-# CHECK-LABEL: name: test_fcmp_oeq_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_oeq_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ogt_s32
-# CHECK-LABEL: name: test_fcmp_ogt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ogt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_oge_s32
-# CHECK-LABEL: name: test_fcmp_oge_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_oge_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_olt_s32
-# CHECK-LABEL: name: test_fcmp_olt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_olt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ole_s32
-# CHECK-LABEL: name: test_fcmp_ole_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ole_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ord_s32
-# CHECK-LABEL: name: test_fcmp_ord_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ord_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ugt_s32
-# CHECK-LABEL: name: test_fcmp_ugt_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ugt_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_uge_s32
-# CHECK-LABEL: name: test_fcmp_uge_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_uge_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ult_s32
-# CHECK-LABEL: name: test_fcmp_ult_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ult_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ule_s32
-# CHECK-LABEL: name: test_fcmp_ule_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ule_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_une_s32
-# CHECK-LABEL: name: test_fcmp_une_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_une_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_uno_s32
-# CHECK-LABEL: name: test_fcmp_uno_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_uno_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_one_s32
-# CHECK-LABEL: name: test_fcmp_one_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_one_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ueq_s32
-# CHECK-LABEL: name: test_fcmp_ueq_s32
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %s0, %s1
+ ; CHECK-LABEL: name: test_fcmp_ueq_s32
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
%1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
- ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_true_s64
-# CHECK-LABEL: name: test_fcmp_true_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_true_s64
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
%1(s64) = COPY %d1
-
%2(s1) = G_FCMP floatpred(true), %0(s64), %1
- ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_false_s64
-# CHECK-LABEL: name: test_fcmp_false_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_false_s64
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
%1(s64) = COPY %d1
-
%2(s1) = G_FCMP floatpred(false), %0(s64), %1
- ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_oeq_s64
-# CHECK-LABEL: name: test_fcmp_oeq_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_oeq_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ogt_s64
-# CHECK-LABEL: name: test_fcmp_ogt_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ogt_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_oge_s64
-# CHECK-LABEL: name: test_fcmp_oge_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_oge_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(oge), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_olt_s64
-# CHECK-LABEL: name: test_fcmp_olt_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_olt_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(olt), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ole_s64
-# CHECK-LABEL: name: test_fcmp_ole_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ole_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ole), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ord_s64
-# CHECK-LABEL: name: test_fcmp_ord_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ord_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ord), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ugt_s64
-# CHECK-LABEL: name: test_fcmp_ugt_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ugt_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_uge_s64
-# CHECK-LABEL: name: test_fcmp_uge_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_uge_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ult_s64
-# CHECK-LABEL: name: test_fcmp_ult_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ult_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ule_s64
-# CHECK-LABEL: name: test_fcmp_ule_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ule_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_une_s64
-# CHECK-LABEL: name: test_fcmp_une_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_une_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(une), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_uno_s64
-# CHECK-LABEL: name: test_fcmp_uno_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_uno_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_one_s64
-# CHECK-LABEL: name: test_fcmp_one_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_one_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(one), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ueq_s64
-# CHECK-LABEL: name: test_fcmp_ueq_s64
legalized: true
regBankSelected: true
selected: false
-# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
bb.0:
liveins: %d0, %d1
+ ; CHECK-LABEL: name: test_fcmp_ueq_s64
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+ ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+ ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+ ; CHECK: %r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, _, implicit %r0
%0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
%1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
- ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
- ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
- ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
-
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
%r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RET]]
-
BX_RET 14, _, implicit %r0
- ; CHECK: BX_RET 14, _, implicit %r0
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
--- |
...
---
-# CHECK-LABEL: name: atomic_memoperands
-# CHECK: %1(s64) = G_LOAD %0(p0) :: (load unordered 8)
-# CHECK: %2(s32) = G_LOAD %0(p0) :: (load monotonic 4)
-# CHECK: %3(s16) = G_LOAD %0(p0) :: (load acquire 2)
-# CHECK: G_STORE %3(s16), %0(p0) :: (store release 2)
-# CHECK: G_STORE %2(s32), %0(p0) :: (store acq_rel 4)
-# CHECK: G_STORE %1(s64), %0(p0) :: (store syncscope("singlethread") seq_cst 8)
name: atomic_memoperands
body: |
bb.0:
+ ; CHECK-LABEL: name: atomic_memoperands
+ ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
+ ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
+ ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
+ ; CHECK: [[LOAD2:%[0-9]+]](s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
+ ; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release 2)
+ ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
+ ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
+ ; CHECK: RET_ReallyLR
%0:_(p0) = COPY %x0
%1:_(s64) = G_LOAD %0(p0) :: (load unordered 8)
%2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
--- |
...
---
-# CHECK-LABEL: name: target_memoperands
-# CHECK: %1(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
-# CHECK: %2(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
-# CHECK: G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
-# CHECK: G_STORE %2(s32), %0(p0) :: ("aarch64-strided-access" store 4)
name: target_memoperands
body: |
bb.0:
+ ; CHECK-LABEL: name: target_memoperands
+ ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
+ ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8)
+ ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
+ ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: ("aarch64-suppress-pair" store 8)
+ ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4)
+ ; CHECK: RET_ReallyLR
%0:_(p0) = COPY %x0
%1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
%2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
--- |
...
---
# Completely invalid code, but it checks that intrinsics round-trip properly.
-# CHECK: %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
name: use_intrin
registers:
- { id: 0, class: _ }
body: |
bb.0:
+ ; CHECK-LABEL: name: use_intrin
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
%0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32)
...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
--- |
define amdgpu_kernel void @flags() {
...
---
-# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
-# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
name: flags
liveins:
body: |
bb.0:
liveins: %sgpr0_sgpr1
+ ; CHECK-LABEL: name: flags
+ ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]] = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+ ; CHECK: [[S_MOV_B64_:%[0-9]+]] = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+ ; CHECK: S_ENDPGM
%0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
%1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses stack object machine operands
# correctly.
- { id: 0, name: b, size: 4, alignment: 4 }
- { id: 1, size: 4, alignment: 4 }
body: |
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
- ; CHECK-NEXT: MOV32mr %stack.0.b, 1, _, 0, _, %0
- ; CHECK-NEXT: MOV32mi %stack.1, 1, _, 0, _, 2
- ; CHECK-NEXT: %1 = MOV32rm %stack.0.b, 1, _, 0, _
bb.0.entry:
+ ; CHECK-LABEL: name: test
+ ; CHECK: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _
+ ; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]]
+ ; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2
+ ; CHECK: [[MOV32rm1:%[0-9]+]] = MOV32rm %stack.0.b, 1, _, 0, _
+ ; CHECK: %eax = COPY [[MOV32rm1]]
+ ; CHECK: RETL %eax
%0 = MOV32rm %fixed-stack.0, 1, _, 0, _
MOV32mr %stack.0.b, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses and prints subregisters index
# operands correctly.
...
---
-# CHECK-LABEL: name: t
-# CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
-# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
-# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
name: t
tracksRegLiveness: true
registers:
body: |
bb.0.entry:
liveins: %edi, %eax
+ ; CHECK-LABEL: name: t
+ ; CHECK: liveins: %edi, %eax
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]] = INSERT_SUBREG %edi, %al, 1
+ ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]] = EXTRACT_SUBREG %eax, 2
+ ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], 1, [[EXTRACT_SUBREG]], 2
+ ; CHECK: RETQ %ax
%0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
%1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
%ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses subregisters in register operands
# correctly.
body: |
bb.0.entry:
liveins: %edi
- ; CHECK: %0 = COPY %edi
- ; CHECK-NEXT: %1 = COPY %0.sub_8bit
+ ; CHECK-LABEL: name: t
+ ; CHECK: liveins: %edi
+ ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+ ; CHECK: [[AND8ri:%[0-9]+]] = AND8ri [[COPY1]], 1, implicit-def %eflags
+ ; CHECK: %al = COPY [[AND8ri]]
+ ; CHECK: RETQ %al
%0 = COPY %edi
%1 = COPY %0.sub_8bit
%2 = AND8ri %1, 1, implicit-def %eflags
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
--- |
...
---
name: test_add_v16i8
-# ALL-LABEL: name: test_add_v16i8
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<16 x s8>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<16 x s8>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<16 x s8>) = G_ADD %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_add_v16i8
+ ; ALL: [[DEF:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
+ ; ALL: [[ADD:%[0-9]+]](<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_ADD %0, %1
...
---
name: test_add_v8i16
-# ALL-LABEL: name: test_add_v8i16
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<8 x s16>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<8 x s16>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<8 x s16>) = G_ADD %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_add_v8i16
+ ; ALL: [[DEF:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
+ ; ALL: [[ADD:%[0-9]+]](<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_ADD %0, %1
...
---
name: test_add_v4i32
-# ALL-LABEL: name: test_add_v4i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<4 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<4 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<4 x s32>) = G_ADD %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_add_v4i32
+ ; ALL: [[DEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
+ ; ALL: [[ADD:%[0-9]+]](<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_ADD %0, %1
...
---
name: test_add_v2i64
-# ALL-LABEL: name: test_add_v2i64
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<2 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<2 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<2 x s64>) = G_ADD %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_add_v2i64
+ ; ALL: [[DEF:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
+ ; ALL: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_ADD %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_and_i1
-# CHECK-LABEL: name: test_and_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
-# CHECK: %0(s32) = COPY %edx
-# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %5(s8) = G_AND %3, %4
-# CHECK-NEXT: %2(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]](s8) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[AND]](s8)
+ ; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_AND %1, %1
...
---
name: test_and_i8
-# CHECK-LABEL: name: test_and_i8
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s8) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s8) = G_AND %0, %0
-# CHECK-NEXT: %al = COPY %1(s8)
-# CHECK-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i8
+ ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
+ ; CHECK: [[AND:%[0-9]+]](s8) = G_AND [[DEF]], [[DEF]]
+ ; CHECK: %al = COPY [[AND]](s8)
+ ; CHECK: RET 0, implicit %al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_AND %0, %0
%al = COPY %1(s8)
...
---
name: test_and_i16
-# CHECK-LABEL: name: test_and_i16
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s16) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s16) = G_AND %0, %0
-# CHECK-NEXT: %ax = COPY %1(s16)
-# CHECK-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i16
+ ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
+ ; CHECK: [[AND:%[0-9]+]](s16) = G_AND [[DEF]], [[DEF]]
+ ; CHECK: %ax = COPY [[AND]](s16)
+ ; CHECK: RET 0, implicit %ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_AND %0, %0
%ax = COPY %1(s16)
...
---
name: test_and_i32
-# CHECK-LABEL: name: test_and_i32
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s32) = G_AND %0, %0
-# CHECK-NEXT: %eax = COPY %1(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i32
+ ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
+ ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[DEF]], [[DEF]]
+ ; CHECK: %eax = COPY [[AND]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = IMPLICIT_DEF
%1(s32) = G_AND %0, %0
%eax = COPY %1(s32)
...
---
name: test_and_i64
-# CHECK-LABEL: name: test_and_i64
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s64) = G_AND %0, %0
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_and_i64
+ ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
+ ; CHECK: [[AND:%[0-9]+]](s64) = G_AND [[DEF]], [[DEF]]
+ ; CHECK: %rax = COPY [[AND]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s64) = IMPLICIT_DEF
%1(s64) = G_AND %0, %0
%rax = COPY %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_cmp_i8
-# CHECK-LABEL: name: test_cmp_i8
alignment: 4
legalized: false
regBankSelected: false
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s8) = COPY %sil
-# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s8), %1
-# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
-# CHECK-NEXT: %eax = COPY %3(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_cmp_i8
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[COPY1:%[0-9]+]](s8) = COPY %sil
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: %eax = COPY [[ZEXT]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s1) = G_ICMP intpred(ult), %0(s8), %1
...
---
name: test_cmp_i16
-# CHECK-LABEL: name: test_cmp_i16
alignment: 4
legalized: false
regBankSelected: false
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
-# CHECK: %0(s16) = COPY %di
-# CHECK-NEXT: %1(s16) = COPY %si
-# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s16), %1
-# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
-# CHECK-NEXT: %eax = COPY %3(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_cmp_i16
+ ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
+ ; CHECK: [[COPY1:%[0-9]+]](s16) = COPY %si
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: %eax = COPY [[ZEXT]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s1) = G_ICMP intpred(ult), %0(s16), %1
...
---
name: test_cmp_i32
-# CHECK-LABEL: name: test_cmp_i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
-# CHECK: %0(s32) = COPY %edi
-# CHECK-NEXT: %1(s32) = COPY %esi
-# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s32), %1
-# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
-# CHECK-NEXT: %eax = COPY %3(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_cmp_i32
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %esi
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: %eax = COPY [[ZEXT]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = COPY %edi
%1(s32) = COPY %esi
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
...
---
name: test_cmp_i64
-# CHECK-LABEL: name: test_cmp_i64
alignment: 4
legalized: false
regBankSelected: false
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
-# CHECK: %0(s64) = COPY %rdi
-# CHECK-NEXT: %1(s64) = COPY %rsi
-# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s64), %1
-# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
-# CHECK-NEXT: %eax = COPY %3(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %rsi
+ ; CHECK-LABEL: name: test_cmp_i64
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %rsi
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: %eax = COPY [[ZEXT]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s64) = COPY %rdi
%1(s64) = COPY %rsi
%2(s1) = G_ICMP intpred(ult), %0(s64), %1
...
---
name: test_cmp_p0
-# CHECK-LABEL: name: test_cmp_p0
alignment: 4
legalized: false
regBankSelected: false
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
-# CHECK: %0(p0) = COPY %rdi
-# CHECK-NEXT: %1(p0) = COPY %rsi
-# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(p0), %1
-# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
-# CHECK-NEXT: %eax = COPY %3(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %rsi
+ ; CHECK-LABEL: name: test_cmp_p0
+ ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]](p0) = COPY %rsi
+ ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: %eax = COPY [[ZEXT]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(p0) = COPY %rdi
%1(p0) = COPY %rsi
%2(s1) = G_ICMP intpred(ult), %0(p0), %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
%r = zext i32 %val to i64
ret i64 %r
}
-
+
define void @test_anyext_i1(i8 %a) {
ret void
}
define void @test_anyext_i32(i32 %val) {
ret void
}
-
+
...
---
name: test_sext_i1
-# CHECK-LABEL: name: test_sext_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
-# CHECK-NEXT: %2(s64) = G_SEXT %1(s1)
-# CHECK-NEXT: %rax = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_sext_i1
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
+ ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[TRUNC]](s1)
+ ; CHECK: %rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_SEXT %1(s1)
...
---
name: test_sext_i8
-# CHECK-LABEL: name: test_sext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s64) = G_SEXT %0(s8)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_sext_i8
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s8)
+ ; CHECK: %rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s64) = G_SEXT %0(s8)
%rax = COPY %1(s64)
...
---
name: test_sext_i16
-# CHECK-LABEL: name: test_sext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s16) = COPY %di
-# CHECK-NEXT: %1(s64) = G_SEXT %0(s16)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_sext_i16
+ ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
+ ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s16)
+ ; CHECK: %rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s16) = COPY %di
%1(s64) = G_SEXT %0(s16)
%rax = COPY %1(s64)
...
---
name: test_sext_i32
-# CHECK-LABEL: name: test_sext_i32
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s32) = COPY %edi
-# CHECK-NEXT: %1(s64) = G_SEXT %0(s32)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_sext_i32
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s32)
+ ; CHECK: %rax = COPY [[SEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s32) = COPY %edi
%1(s64) = G_SEXT %0(s32)
%rax = COPY %1(s64)
...
---
name: test_zext_i1
-# CHECK-LABEL: name: test_zext_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
-# CHECK-NEXT: %2(s64) = G_ZEXT %1(s1)
-# CHECK-NEXT: %rax = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_zext_i1
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
+ ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[TRUNC]](s1)
+ ; CHECK: %rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ZEXT %1(s1)
...
---
name: test_zext_i8
-# CHECK-LABEL: name: test_zext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s64) = G_ZEXT %0(s8)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_zext_i8
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s8)
+ ; CHECK: %rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s64) = G_ZEXT %0(s8)
%rax = COPY %1(s64)
...
---
name: test_zext_i16
-# CHECK-LABEL: name: test_zext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s16) = COPY %di
-# CHECK-NEXT: %1(s64) = G_ZEXT %0(s16)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_zext_i16
+ ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
+ ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s16)
+ ; CHECK: %rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s16) = COPY %di
%1(s64) = G_ZEXT %0(s16)
%rax = COPY %1(s64)
...
---
name: test_zext_i32
-# CHECK-LABEL: name: test_zext_i32
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s32) = COPY %edi
-# CHECK-NEXT: %1(s64) = G_ZEXT %0(s32)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_zext_i32
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s32)
+ ; CHECK: %rax = COPY [[ZEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s32) = COPY %edi
%1(s64) = G_ZEXT %0(s32)
%rax = COPY %1(s64)
...
---
name: test_anyext_i1
-# CHECK-LABEL: name: test_anyext_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
-# CHECK-NEXT: %2(s64) = G_ANYEXT %1(s1)
-# CHECK-NEXT: %rax = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_anyext_i1
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s1)
+ ; CHECK: %rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ANYEXT %1(s1)
...
---
name: test_anyext_i8
-# CHECK-LABEL: name: test_anyext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s8) = COPY %dil
-# CHECK-NEXT: %1(s64) = G_ANYEXT %0(s8)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_anyext_i8
+ ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: %rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s64) = G_ANYEXT %0(s8)
%rax = COPY %1(s64)
...
---
name: test_anyext_i16
-# CHECK-LABEL: name: test_anyext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s16) = COPY %di
-# CHECK-NEXT: %1(s64) = G_ANYEXT %0(s16)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_anyext_i16
+ ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s16)
+ ; CHECK: %rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s16) = COPY %di
%1(s64) = G_ANYEXT %0(s16)
%rax = COPY %1(s64)
...
---
name: test_anyext_i32
-# CHECK-LABEL: name: test_anyext_i32
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# CHECK: %0(s32) = COPY %edi
-# CHECK-NEXT: %1(s64) = G_ANYEXT %0(s32)
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; CHECK-LABEL: name: test_anyext_i32
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK: %rax = COPY [[ANYEXT]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s32) = COPY %edi
%1(s64) = G_ANYEXT %0(s32)
%rax = COPY %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_fadd_float
-# CHECK-LABEL: name: test_fadd_float
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = COPY %xmm0
-# CHECK-NEXT: %1(s32) = COPY %xmm1
-# CHECK-NEXT: %2(s32) = G_FADD %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fadd_float
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
+ ; CHECK: [[FADD:%[0-9]+]](s32) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FADD]](s32)
+ ; CHECK: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FADD %0, %1
...
---
name: test_fadd_double
-# CHECK-LABEL: name: test_fadd_double
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = COPY %xmm0
-# CHECK-NEXT: %1(s64) = COPY %xmm1
-# CHECK-NEXT: %2(s64) = G_FADD %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fadd_double
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
+ ; CHECK: [[FADD:%[0-9]+]](s64) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FADD]](s64)
+ ; CHECK: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FADD %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_fdiv_float
-# CHECK-LABEL: name: test_fdiv_float
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = COPY %xmm0
-# CHECK-NEXT: %1(s32) = COPY %xmm1
-# CHECK-NEXT: %2(s32) = G_FDIV %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fdiv_float
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
+ ; CHECK: [[FDIV:%[0-9]+]](s32) = G_FDIV [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FDIV]](s32)
+ ; CHECK: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FDIV %0, %1
...
---
name: test_fdiv_double
-# CHECK-LABEL: name: test_fdiv_double
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = COPY %xmm0
-# CHECK-NEXT: %1(s64) = COPY %xmm1
-# CHECK-NEXT: %2(s64) = G_FDIV %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fdiv_double
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
+ ; CHECK: [[FDIV:%[0-9]+]](s64) = G_FDIV [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FDIV]](s64)
+ ; CHECK: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FDIV %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_fmul_float
-# CHECK-LABEL: name: test_fmul_float
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = COPY %xmm0
-# CHECK-NEXT: %1(s32) = COPY %xmm1
-# CHECK-NEXT: %2(s32) = G_FMUL %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fmul_float
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
+ ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FMUL]](s32)
+ ; CHECK: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FMUL %0, %1
...
---
name: test_fmul_double
-# CHECK-LABEL: name: test_fmul_double
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = COPY %xmm0
-# CHECK-NEXT: %1(s64) = COPY %xmm1
-# CHECK-NEXT: %2(s64) = G_FMUL %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fmul_double
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
+ ; CHECK: [[FMUL:%[0-9]+]](s64) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FMUL]](s64)
+ ; CHECK: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FMUL %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
--- |
...
---
name: test
-# ALL-LABEL: name: test
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s32) = COPY %xmm0
-# ALL-NEXT: %1(s64) = G_FPEXT %0(s32)
-# ALL-NEXT: %xmm0 = COPY %1(s64)
-# ALL-NEXT: RET 0, implicit %xmm0
body: |
bb.1.entry:
liveins: %xmm0
+ ; ALL-LABEL: name: test
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %xmm0
+ ; ALL: [[FPEXT:%[0-9]+]](s64) = G_FPEXT [[COPY]](s32)
+ ; ALL: %xmm0 = COPY [[FPEXT]](s64)
+ ; ALL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s64) = G_FPEXT %0(s32)
%xmm0 = COPY %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_fsub_float
-# CHECK-LABEL: name: test_fsub_float
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = COPY %xmm0
-# CHECK-NEXT: %1(s32) = COPY %xmm1
-# CHECK-NEXT: %2(s32) = G_FSUB %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fsub_float
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
+ ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FSUB]](s32)
+ ; CHECK: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
%1(s32) = COPY %xmm1
%2(s32) = G_FSUB %0, %1
...
---
name: test_fsub_double
-# CHECK-LABEL: name: test_fsub_double
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = COPY %xmm0
-# CHECK-NEXT: %1(s64) = COPY %xmm1
-# CHECK-NEXT: %2(s64) = G_FSUB %0, %1
-# CHECK-NEXT: %xmm0 = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %xmm0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; CHECK-LABEL: name: test_fsub_double
+ ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
+ ; CHECK: [[FSUB:%[0-9]+]](s64) = G_FSUB [[COPY]], [[COPY1]]
+ ; CHECK: %xmm0 = COPY [[FSUB]](s64)
+ ; CHECK: RET 0, implicit %xmm0
%0(s64) = COPY %xmm0
%1(s64) = COPY %xmm1
%2(s64) = G_FSUB %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_gep_i8
-# CHECK-LABEL: name: test_gep_i8
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(p0) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s8) = G_CONSTANT i8 20
-# CHECK-NEXT: %3(s32) = G_SEXT %1(s8)
-# CHECK-NEXT: %2(p0) = G_GEP %0, %3(s32)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i8
+ ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]](s8) = G_CONSTANT i8 20
+ ; CHECK: [[SEXT:%[0-9]+]](s32) = G_SEXT [[C]](s8)
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[SEXT]](s32)
+ ; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s8) = G_CONSTANT i8 20
%2(p0) = G_GEP %0, %1(s8)
...
---
name: test_gep_i16
-# CHECK-LABEL: name: test_gep_i16
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(p0) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s16) = G_CONSTANT i16 20
-# CHECK-NEXT: %3(s32) = G_SEXT %1(s16)
-# CHECK-NEXT: %2(p0) = G_GEP %0, %3(s32)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i16
+ ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]](s16) = G_CONSTANT i16 20
+ ; CHECK: [[SEXT:%[0-9]+]](s32) = G_SEXT [[C]](s16)
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[SEXT]](s32)
+ ; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s16) = G_CONSTANT i16 20
%2(p0) = G_GEP %0, %1(s16)
...
---
name: test_gep_i32
-# CHECK-LABEL: name: test_gep_i32
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(p0) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s32) = G_CONSTANT i32 20
-# CHECK-NEXT: %2(p0) = G_GEP %0, %1(s32)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i32
+ ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 20
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[C]](s32)
+ ; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
%2(p0) = G_GEP %0, %1(s32)
...
---
name: test_gep_i64
-# CHECK-LABEL: name: test_gep_i64
legalized: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(p0) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s64) = G_CONSTANT i64 20
-# CHECK-NEXT: %2(p0) = G_GEP %0, %1(s64)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i64
+ ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 20
+ ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[C]](s64)
+ ; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = G_CONSTANT i64 20
%2(p0) = G_GEP %0, %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
...
---
name: test_insert_128
-# ALL-LABEL: name: test_insert_128
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<16 x s32>) = COPY %zmm0
-# ALL-NEXT: %1(<4 x s32>) = COPY %xmm1
-# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
-# ALL-NEXT: %zmm0 = COPY %2(<16 x s32>)
-# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %ymm1
+ ; ALL-LABEL: name: test_insert_128
+ ; ALL: [[COPY:%[0-9]+]](<16 x s32>) = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]](<4 x s32>) = COPY %xmm1
+ ; ALL: [[INSERT:%[0-9]+]](<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0
+ ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>)
+ ; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
...
---
name: test_insert_256
-# ALL-LABEL: name: test_insert_256
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<16 x s32>) = COPY %zmm0
-# ALL-NEXT: %1(<8 x s32>) = COPY %ymm1
-# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<8 x s32>), 0
-# ALL-NEXT: %zmm0 = COPY %2(<16 x s32>)
-# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %ymm1
+ ; ALL-LABEL: name: test_insert_256
+ ; ALL: [[COPY:%[0-9]+]](<16 x s32>) = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]](<8 x s32>) = COPY %ymm1
+ ; ALL: [[INSERT:%[0-9]+]](<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0
+ ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>)
+ ; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_or_i1
-# CHECK-LABEL: name: test_or_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
-# CHECK: %0(s32) = COPY %edx
-# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %5(s8) = G_OR %3, %4
-# CHECK-NEXT: %2(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[OR:%[0-9]+]](s8) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[OR]](s8)
+ ; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_OR %1, %1
...
---
name: test_or_i8
-# CHECK-LABEL: name: test_or_i8
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s8) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s8) = G_OR %0, %0
-# CHECK-NEXT: %al = COPY %1(s8)
-# CHECK-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i8
+ ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
+ ; CHECK: [[OR:%[0-9]+]](s8) = G_OR [[DEF]], [[DEF]]
+ ; CHECK: %al = COPY [[OR]](s8)
+ ; CHECK: RET 0, implicit %al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_OR %0, %0
%al = COPY %1(s8)
...
---
name: test_or_i16
-# CHECK-LABEL: name: test_or_i16
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s16) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s16) = G_OR %0, %0
-# CHECK-NEXT: %ax = COPY %1(s16)
-# CHECK-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i16
+ ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
+ ; CHECK: [[OR:%[0-9]+]](s16) = G_OR [[DEF]], [[DEF]]
+ ; CHECK: %ax = COPY [[OR]](s16)
+ ; CHECK: RET 0, implicit %ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_OR %0, %0
%ax = COPY %1(s16)
...
---
name: test_or_i32
-# CHECK-LABEL: name: test_or_i32
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s32) = G_OR %0, %0
-# CHECK-NEXT: %eax = COPY %1(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i32
+ ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
+ ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[DEF]], [[DEF]]
+ ; CHECK: %eax = COPY [[OR]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = IMPLICIT_DEF
%1(s32) = G_OR %0, %0
%eax = COPY %1(s32)
...
---
name: test_or_i64
-# CHECK-LABEL: name: test_or_i64
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s64) = G_OR %0, %0
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_or_i64
+ ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
+ ; CHECK: [[OR:%[0-9]+]](s64) = G_OR [[DEF]], [[DEF]]
+ ; CHECK: %rax = COPY [[OR]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s64) = IMPLICIT_DEF
%1(s64) = G_OR %0, %0
%rax = COPY %1(s64)
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
--- |
...
---
name: test_i1
-# ALL-LABEL: name: test_i1
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %edx, %esi
-
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s1) = COPY %esi
-# ALL-NEXT: %2(s1) = COPY %edx
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: %8(s8) = G_ANYEXT %1(s1)
-# ALL-NEXT: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL: %9(s8) = G_ANYEXT %2(s1)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %7(s8) = G_PHI %8(s8), %bb.1.cond.true, %9(s8), %bb.2.cond.false
-# ALL-NEXT: %5(s1) = G_TRUNC %7(s8)
-# ALL-NEXT: %6(s8) = G_ZEXT %5(s1)
-# ALL-NEXT: %al = COPY %6(s8)
-# ALL-NEXT: RET 0, implicit %al
+
+
+
+
body: |
+ ; ALL-LABEL: name: test_i1
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %edx, %esi
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s1) = COPY %esi
+ ; ALL: [[COPY2:%[0-9]+]](s1) = COPY %edx
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: [[ANYEXT:%[0-9]+]](s8) = G_ANYEXT [[COPY1]](s1)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: [[ANYEXT1:%[0-9]+]](s8) = G_ANYEXT [[COPY2]](s1)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s8) = G_PHI [[ANYEXT]](s8), %bb.1.cond.true, [[ANYEXT1]](s8), %bb.2.cond.false
+ ; ALL: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[PHI]](s8)
+ ; ALL: [[ZEXT:%[0-9]+]](s8) = G_ZEXT [[TRUNC]](s1)
+ ; ALL: %al = COPY [[ZEXT]](s8)
+ ; ALL: RET 0, implicit %al
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %edx, %esi
...
---
name: test_i8
-# ALL-LABEL: name: test_i8
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %edx, %esi
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s8) = COPY %sil
-# ALL-NEXT: %2(s8) = COPY %edx
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s8) = G_PHI %1(s8), %bb.1.cond.true, %2(s8), %bb.2.cond.false
-# ALL-NEXT: %al = COPY %5(s8)
-# ALL-NEXT: RET 0, implicit %al
+
+
+
body: |
+ ; ALL-LABEL: name: test_i8
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %edx, %esi
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s8) = COPY %sil
+ ; ALL: [[COPY2:%[0-9]+]](s8) = COPY %edx
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s8) = G_PHI [[COPY1]](s8), %bb.1.cond.true, [[COPY2]](s8), %bb.2.cond.false
+ ; ALL: %al = COPY [[PHI]](s8)
+ ; ALL: RET 0, implicit %al
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %edx, %esi
...
---
name: test_i16
-# ALL-LABEL: name: test_i16
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %edx, %esi
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s16) = COPY %si
-# ALL-NEXT: %2(s16) = COPY %edx
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s16) = G_PHI %1(s16), %bb.1.cond.true, %2(s16), %bb.2.cond.false
-# ALL-NEXT: %ax = COPY %5(s16)
-# ALL-NEXT: RET 0, implicit %ax
+
+
+
body: |
+ ; ALL-LABEL: name: test_i16
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %edx, %esi
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s16) = COPY %si
+ ; ALL: [[COPY2:%[0-9]+]](s16) = COPY %edx
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s16) = G_PHI [[COPY1]](s16), %bb.1.cond.true, [[COPY2]](s16), %bb.2.cond.false
+ ; ALL: %ax = COPY [[PHI]](s16)
+ ; ALL: RET 0, implicit %ax
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %edx, %esi
...
---
name: test_i32
-# ALL-LABEL: name: test_i32
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %edx, %esi
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s32) = COPY %esi
-# ALL-NEXT: %2(s32) = COPY %edx
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
-# ALL-NEXT: %eax = COPY %5(s32)
-# ALL-NEXT: RET 0, implicit %eax
+
+
+
body: |
+ ; ALL-LABEL: name: test_i32
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %edx, %esi
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s32) = COPY %esi
+ ; ALL: [[COPY2:%[0-9]+]](s32) = COPY %edx
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
+ ; ALL: %eax = COPY [[PHI]](s32)
+ ; ALL: RET 0, implicit %eax
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %edx, %esi
...
---
name: test_i64
-# ALL-LABEL: name: test_i64
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %rdx, %rsi
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s64) = COPY %rsi
-# ALL-NEXT: %2(s64) = COPY %rdx
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s64) = G_PHI %1(s64), %bb.1.cond.true, %2(s64), %bb.2.cond.false
-# ALL-NEXT: %rax = COPY %5(s64)
-# ALL-NEXT: RET 0, implicit %rax
+
+
+
body: |
+ ; ALL-LABEL: name: test_i64
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %rdx, %rsi
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s64) = COPY %rsi
+ ; ALL: [[COPY2:%[0-9]+]](s64) = COPY %rdx
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
+ ; ALL: %rax = COPY [[PHI]](s64)
+ ; ALL: RET 0, implicit %rax
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %rdx, %rsi
...
---
name: test_float
-# ALL-LABEL: name: test_float
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %xmm0, %xmm1
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s32) = COPY %xmm0
-# ALL-NEXT: %2(s32) = COPY %xmm1
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
-# ALL-NEXT: %xmm0 = COPY %5(s32)
-# ALL-NEXT: RET 0, implicit %xmm0
+
+
+
body: |
+ ; ALL-LABEL: name: test_float
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %xmm0, %xmm1
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s32) = COPY %xmm0
+ ; ALL: [[COPY2:%[0-9]+]](s32) = COPY %xmm1
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
+ ; ALL: %xmm0 = COPY [[PHI]](s32)
+ ; ALL: RET 0, implicit %xmm0
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %xmm0, %xmm1
...
---
name: test_double
-# ALL-LABEL: name: test_double
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# ALL: bb.0.entry:
-# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
-# ALL-NEXT: liveins: %edi, %xmm0, %xmm1
-# ALL: %0(s32) = COPY %edi
-# ALL-NEXT: %1(s64) = COPY %xmm0
-# ALL-NEXT: %2(s64) = COPY %xmm1
-# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
-# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
-# ALL-NEXT: G_BRCOND %4(s1), %bb.1.cond.true
-# ALL-NEXT: G_BR %bb.2.cond.false
-
-# ALL-LABEL: bb.1.cond.true:
-# ALL: G_BR %bb.3.cond.end
-
-# ALL-LABEL: bb.2.cond.false:
-# ALL-NEXT: successors: %bb.3.cond.end(0x80000000)
-
-# ALL-LABEL: bb.3.cond.end:
-# ALL-NEXT: %5(s64) = G_PHI %1(s64), %bb.1.cond.true, %2(s64), %bb.2.cond.false
-# ALL-NEXT: %xmm0 = COPY %5(s64)
-# ALL-NEXT: RET 0, implicit %xmm0
+
+
+
body: |
+ ; ALL-LABEL: name: test_double
+ ; ALL: bb.0.entry:
+ ; ALL: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
+ ; ALL: liveins: %edi, %xmm0, %xmm1
+ ; ALL: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]](s64) = COPY %xmm0
+ ; ALL: [[COPY2:%[0-9]+]](s64) = COPY %xmm1
+ ; ALL: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
+ ; ALL: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+ ; ALL: G_BRCOND [[ICMP]](s1), %bb.1.cond.true
+ ; ALL: G_BR %bb.2.cond.false
+ ; ALL: bb.1.cond.true:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: G_BR %bb.3.cond.end
+ ; ALL: bb.2.cond.false:
+ ; ALL: successors: %bb.3.cond.end(0x80000000)
+ ; ALL: bb.3.cond.end:
+ ; ALL: [[PHI:%[0-9]+]](s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
+ ; ALL: %xmm0 = COPY [[PHI]](s64)
+ ; ALL: RET 0, implicit %xmm0
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
liveins: %edi, %xmm0, %xmm1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
--- |
...
---
name: test_sub_v16i8
-# ALL-LABEL: name: test_sub_v16i8
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<16 x s8>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<16 x s8>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<16 x s8>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_sub_v16i8
+ ; ALL: [[DEF:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_SUB %0, %1
...
---
name: test_sub_v8i16
-# ALL-LABEL: name: test_sub_v8i16
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<8 x s16>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<8 x s16>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<8 x s16>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_sub_v8i16
+ ; ALL: [[DEF:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_SUB %0, %1
...
---
name: test_sub_v4i32
-# ALL-LABEL: name: test_sub_v4i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<4 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<4 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<4 x s32>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_sub_v4i32
+ ; ALL: [[DEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_SUB %0, %1
...
---
name: test_sub_v2i64
-# ALL-LABEL: name: test_sub_v2i64
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<2 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<2 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<2 x s64>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
+ ; ALL-LABEL: name: test_sub_v2i64
+ ; ALL: [[DEF:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_SUB %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
# TODO: add tests for additional configuration after the legalization supported
--- |
...
---
name: test_sub_v32i8
-# ALL-LABEL: name: test_sub_v32i8
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX2: %0(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT: %1(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT: %2(<32 x s8>) = G_SUB %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_sub_v32i8
+ ; ALL: [[DEF:%[0-9]+]](<32 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<32 x s8>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_SUB %0, %1
...
---
name: test_sub_v16i16
-# ALL-LABEL: name: test_sub_v16i16
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX2: %0(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT: %1(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT: %2(<16 x s16>) = G_SUB %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_sub_v16i16
+ ; ALL: [[DEF:%[0-9]+]](<16 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<16 x s16>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_SUB %0, %1
...
---
name: test_sub_v8i32
-# ALL-LABEL: name: test_sub_v8i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX2: %0(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT: %1(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT: %2(<8 x s32>) = G_SUB %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_sub_v8i32
+ ; ALL: [[DEF:%[0-9]+]](<8 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<8 x s32>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_SUB %0, %1
...
---
name: test_sub_v4i64
-# ALL-LABEL: name: test_sub_v4i64
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX2: %0(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT: %1(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT: %2(<4 x s64>) = G_SUB %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_sub_v4i64
+ ; ALL: [[DEF:%[0-9]+]](<4 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<4 x s64>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_SUB %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
# TODO: add tests for additional configuration after the legalization supported
--- |
...
---
name: test_sub_v64i8
-# ALL-LABEL: name: test_sub_v64i8
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX512BW: %0(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2(<64 x s8>) = G_SUB %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_sub_v64i8
+ ; ALL: [[DEF:%[0-9]+]](<64 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<64 x s8>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_SUB %0, %1
...
---
name: test_sub_v32i16
-# ALL-LABEL: name: test_sub_v32i16
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX512BW: %0(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2(<32 x s16>) = G_SUB %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_sub_v32i16
+ ; ALL: [[DEF:%[0-9]+]](<32 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<32 x s16>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_SUB %0, %1
...
---
name: test_sub_v16i32
-# ALL-LABEL: name: test_sub_v16i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<16 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<16 x s32>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<16 x s32>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_sub_v16i32
+ ; ALL: [[DEF:%[0-9]+]](<16 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<16 x s32>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_SUB %0, %1
...
---
name: test_sub_v8i64
-# ALL-LABEL: name: test_sub_v8i64
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(<8 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %1(<8 x s64>) = IMPLICIT_DEF
-# ALL-NEXT: %2(<8 x s64>) = G_SUB %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_sub_v8i64
+ ; ALL: [[DEF:%[0-9]+]](<8 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]](<8 x s64>) = IMPLICIT_DEF
+ ; ALL: [[SUB:%[0-9]+]](<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
+ ; ALL: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_SUB %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_sub_i1
-# CHECK-LABEL: name: test_sub_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
-# CHECK: %0(s32) = COPY %edx
-# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %5(s8) = G_SUB %3, %4
-# CHECK-NEXT: %2(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_sub_i1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[SUB:%[0-9]+]](s8) = G_SUB [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[SUB]](s8)
+ ; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_SUB %1, %1
...
---
name: test_sub_i32
-# CHECK-LABEL: name: test_sub_i32
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: %0(s32) = COPY %edi
-# CHECK-NEXT: %1(s32) = COPY %esi
-# CHECK-NEXT: %2(s32) = G_SUB %0, %1
-# CHECK-NEXT: %eax = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_sub_i32
+ ; CHECK: liveins: %edi, %esi
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %esi
+ ; CHECK: [[SUB:%[0-9]+]](s32) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK: %eax = COPY [[SUB]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = COPY %edi
%1(s32) = COPY %esi
%2(s32) = G_SUB %0, %1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
...
---
name: test_xor_i1
-# CHECK-LABEL: name: test_xor_i1
alignment: 4
legalized: false
regBankSelected: false
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
-# CHECK: %0(s32) = COPY %edx
-# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %5(s8) = G_XOR %3, %4
-# CHECK-NEXT: %2(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i1
+ ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
+ ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[XOR:%[0-9]+]](s8) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[XOR]](s8)
+ ; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_XOR %1, %1
...
---
name: test_xor_i8
-# CHECK-LABEL: name: test_xor_i8
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s8) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s8) = G_XOR %0, %0
-# CHECK-NEXT: %al = COPY %1(s8)
-# CHECK-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i8
+ ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
+ ; CHECK: [[XOR:%[0-9]+]](s8) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK: %al = COPY [[XOR]](s8)
+ ; CHECK: RET 0, implicit %al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_XOR %0, %0
%al = COPY %1(s8)
...
---
name: test_xor_i16
-# CHECK-LABEL: name: test_xor_i16
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s16) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s16) = G_XOR %0, %0
-# CHECK-NEXT: %ax = COPY %1(s16)
-# CHECK-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i16
+ ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
+ ; CHECK: [[XOR:%[0-9]+]](s16) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK: %ax = COPY [[XOR]](s16)
+ ; CHECK: RET 0, implicit %ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_XOR %0, %0
%ax = COPY %1(s16)
...
---
name: test_xor_i32
-# CHECK-LABEL: name: test_xor_i32
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s32) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s32) = G_XOR %0, %0
-# CHECK-NEXT: %eax = COPY %1(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i32
+ ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
+ ; CHECK: [[XOR:%[0-9]+]](s32) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK: %eax = COPY [[XOR]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = IMPLICIT_DEF
%1(s32) = G_XOR %0, %0
%eax = COPY %1(s32)
...
---
name: test_xor_i64
-# CHECK-LABEL: name: test_xor_i64
alignment: 4
legalized: false
regBankSelected: false
fixedStack:
stack:
constants:
-# CHECK: %0(s64) = IMPLICIT_DEF
-# CHECK-NEXT: %1(s64) = G_XOR %0, %0
-# CHECK-NEXT: %rax = COPY %1(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_xor_i64
+ ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
+ ; CHECK: [[XOR:%[0-9]+]](s64) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK: %rax = COPY [[XOR]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s64) = IMPLICIT_DEF
%1(s64) = G_XOR %0, %0
%rax = COPY %1(s64)
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