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[InstCombine] Address a couple stylistic issues pointed out by reviewer [NFC]
authorPhilip Reames <listmail@philipreames.com>
Fri, 15 Feb 2019 21:31:39 +0000 (21:31 +0000)
committerPhilip Reames <listmail@philipreames.com>
Fri, 15 Feb 2019 21:31:39 +0000 (21:31 +0000)
Better addressing comments from https://reviews.llvm.org/D58290.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354171 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

index 58da7eb..b857741 100644 (file)
@@ -26,8 +26,7 @@ bool isIdempotentRMW(AtomicRMWInst& RMWI) {
     // TODO: Handle fadd, fsub?
     return false;
 
-  AtomicRMWInst::BinOp Op = RMWI.getOperation();
-  switch(Op) {
+  switch(RMWI.getOperation()) {
     case AtomicRMWInst::Add:
     case AtomicRMWInst::Sub:
     case AtomicRMWInst::Or:
@@ -55,12 +54,12 @@ bool isSaturating(AtomicRMWInst& RMWI) {
   if(!C)
     return false;
 
-  AtomicRMWInst::BinOp Op = RMWI.getOperation();
-  switch(Op) {
+  switch(RMWI.getOperation()) {
   default:
     // TODO: fadd, fsub w/Nan
-    // Note: We avoid listing xchg to prevent transform cycles.
     return false;
+  case AtomicRMWInst::Xchg:
+    return true;
   case AtomicRMWInst::Or:
     return C->isAllOnesValue();
   case AtomicRMWInst::And:
@@ -87,7 +86,8 @@ Instruction *InstCombiner::visitAtomicRMWInst(AtomicRMWInst &RMWI) {
 
   // Any atomicrmw op which produces a known result in memory can be
   // replaced w/an atomicrmw xchg.
-  if (isSaturating(RMWI)) {
+  if (isSaturating(RMWI) &&
+      RMWI.getOperation() != AtomicRMWInst::Xchg) {
     RMWI.setOperation(AtomicRMWInst::Xchg);
     return &RMWI;
   }