#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H
#define LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H
-#include "llvm/MC/MCInstPrinter.h"
#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
const MCSubtargetInfo &STI) const override;
public:
- WebAssemblyMCCodeEmitter(const MCInstrInfo &mcii)
- : MCII(mcii) {}
+ WebAssemblyMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
};
} // end anonymous namespace
support::endian::Writer<support::little>(OS).write<uint64_t>(0);
Fixups.push_back(MCFixup::create(
(1 + MCII.get(MI.getOpcode()).isVariadic() + i) * sizeof(uint64_t),
- MO.getExpr(), STI.getTargetTriple().isArch64Bit() ? FK_Data_8 : FK_Data_4,
+ MO.getExpr(),
+ STI.getTargetTriple().isArch64Bit() ? FK_Data_8 : FK_Data_4,
MI.getLoc()));
++MCNumFixups;
} else {
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI) {
- assert(SyntaxVariant == 0);
+ assert(SyntaxVariant == 0 && "WebAssembly only has one syntax variant");
return new WebAssemblyInstPrinter(MAI, MII, MRI);
}
//===----------------------------------------------------------------------===//
#include "WebAssembly.h"
+#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
-#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/Debug.h"
auto &MRI = MF.getRegInfo();
for (auto &MBB : MF) {
- for (auto MII = MBB.begin(); MII != MBB.end(); ) {
+ for (auto MII = MBB.begin(); MII != MBB.end();) {
MachineInstr *MI = &*MII++;
if (MI->getOpcode() != WebAssembly::BR_UNLESS)
continue;
assert(MRI.hasOneDef(Cond));
MachineInstr *Def = MRI.getVRegDef(Cond);
switch (Def->getOpcode()) {
- using namespace WebAssembly;
+ using namespace WebAssembly;
case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
if (!Inverted) {
unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
MFI.stackifyVReg(ZeroReg);
- BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg)
+ BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32),
+ ZeroReg)
.addImm(0);
unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
MFI.stackifyVReg(Tmp);
MachineOperand &MO = MI.getOperand(0);
unsigned OldReg = MO.getReg();
// TODO: Handle SP/physregs
- if (OldReg == MI.getOperand(3).getReg()
- && TargetRegisterInfo::isVirtualRegister(MI.getOperand(3).getReg())) {
+ if (OldReg == MI.getOperand(3).getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MI.getOperand(3).getReg())) {
Changed = true;
unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
MO.setReg(NewReg);
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "llvm/ADT/SCCIterator.h"
-#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"