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i965: Disable register spilling on gen6 until it's fixed.
author
Eric Anholt
<eric@anholt.net>
Tue, 26 Oct 2010 21:49:38 +0000
(14:49 -0700)
committer
Eric Anholt
<eric@anholt.net>
Tue, 26 Oct 2010 22:07:25 +0000
(15:07 -0700)
Avoids GPU hang on glsl-fs-convolution-1.
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
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diff --git
a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index
d7acc30
..
bbb210c
100644
(file)
--- a/
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@
-225,7
+225,7
@@
fs_visitor::assign_regs()
* loop back into here to try again.
*/
int reg = choose_spill_reg(g);
- if (reg == -1) {
+ if (reg == -1
|| intel->gen >= 6
) {
this->fail = true;
} else {
spill_reg(reg);