mlxsw: Query UTC sec and nsec PCI offsets and values

Query UTC sec and nsec PCI offsets during the pci_init(), to be able to
read UTC time later.

Implement functions to read UTC seconds and nanoseconds from the offset
which was read as part of initialization.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c
index aef3961..7c93bd0 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/core.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.c
@@ -3335,6 +3335,18 @@ u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core)
 }
 EXPORT_SYMBOL(mlxsw_core_read_frc_l);
 
+u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core)
+{
+       return mlxsw_core->bus->read_utc_sec(mlxsw_core->bus_priv);
+}
+EXPORT_SYMBOL(mlxsw_core_read_utc_sec);
+
+u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core)
+{
+       return mlxsw_core->bus->read_utc_nsec(mlxsw_core->bus_priv);
+}
+EXPORT_SYMBOL(mlxsw_core_read_utc_nsec);
+
 bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core)
 {
        return mlxsw_core->driver->sdq_supports_cqe_v2;

diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h
index 6c332bb..cfc365b 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -438,6 +438,9 @@ int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core);
 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core);
 
+u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core);
+u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core);
+
 bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core);
 
 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core);
@@ -479,6 +482,8 @@ struct mlxsw_bus {
                        u8 *p_status);
        u32 (*read_frc_h)(void *bus_priv);
        u32 (*read_frc_l)(void *bus_priv);
+       u32 (*read_utc_sec)(void *bus_priv);
+       u32 (*read_utc_nsec)(void *bus_priv);
        u8 features;
 };
 

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index f1cd560..0e4bd63 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -103,6 +103,8 @@ struct mlxsw_pci {
        struct pci_dev *pdev;
        u8 __iomem *hw_addr;
        u64 free_running_clock_offset;
+       u64 utc_sec_offset;
+       u64 utc_nsec_offset;
        struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
        u32 doorbell_offset;
        struct mlxsw_core *core;
@@ -1537,6 +1539,24 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
        mlxsw_pci->free_running_clock_offset =
                mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
 
+       if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) {
+               dev_err(&pdev->dev, "Unsupported UTC sec BAR queried from hw\n");
+               err = -EINVAL;
+               goto err_utc_sec_bar;
+       }
+
+       mlxsw_pci->utc_sec_offset =
+               mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox);
+
+       if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) {
+               dev_err(&pdev->dev, "Unsupported UTC nsec BAR queried from hw\n");
+               err = -EINVAL;
+               goto err_utc_nsec_bar;
+       }
+
+       mlxsw_pci->utc_nsec_offset =
+               mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox);
+
        num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
        err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
        if (err)
@@ -1601,6 +1621,8 @@ err_query_resources:
 err_boardinfo:
        mlxsw_pci_fw_area_fini(mlxsw_pci);
 err_fw_area_init:
+err_utc_nsec_bar:
+err_utc_sec_bar:
 err_fr_rn_clk_bar:
 err_doorbell_page_bar:
 err_iface_rev:
@@ -1830,6 +1852,20 @@ static u32 mlxsw_pci_read_frc_l(void *bus_priv)
        return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_l);
 }
 
+static u32 mlxsw_pci_read_utc_sec(void *bus_priv)
+{
+       struct mlxsw_pci *mlxsw_pci = bus_priv;
+
+       return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_sec_offset);
+}
+
+static u32 mlxsw_pci_read_utc_nsec(void *bus_priv)
+{
+       struct mlxsw_pci *mlxsw_pci = bus_priv;
+
+       return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_nsec_offset);
+}
+
 static const struct mlxsw_bus mlxsw_pci_bus = {
        .kind                   = "pci",
        .init                   = mlxsw_pci_init,
@@ -1839,6 +1875,8 @@ static const struct mlxsw_bus mlxsw_pci_bus = {
        .cmd_exec               = mlxsw_pci_cmd_exec,
        .read_frc_h             = mlxsw_pci_read_frc_h,
        .read_frc_l             = mlxsw_pci_read_frc_l,
+       .read_utc_sec           = mlxsw_pci_read_utc_sec,
+       .read_utc_nsec          = mlxsw_pci_read_utc_nsec,
        .features               = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
 };