PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160206);
- else
- PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
+ PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
}
//LO calibration setting
RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
- else
- PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
+ PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
//One shot, path A LOK & IQK
RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
TX0_A = (X * Oldval_0) >> 8;
RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT24, ((X* Oldval_0>>7) & 0x1));
- else
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
+ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
Y = result[final_candidate][1];
if ((Y & 0x00000200) != 0)
RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
- if(IS_HARDWARE_TYPE_8192D(pAdapter)/*&&is2T*/)
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT26, ((Y* Oldval_0>>7) & 0x1));
- else
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
+ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
if(bTxOnly)
{
TX1_A = (X * Oldval_1) >> 8;
RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT28, ((X* Oldval_1>>7) & 0x1));
- else
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
+ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
Y = result[final_candidate][5];
if ((Y & 0x00000200) != 0)
RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT30, ((Y* Oldval_1>>7) & 0x1));
- else
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
+ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
if(bTxOnly)
return;
IN u1Byte c2
)
{
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- return phy_SimularityCompare_92D(pAdapter, result, c1, c2);
- else
- return phy_SimularityCompare_92C(pAdapter, result, c1, c2);
-
+ return phy_SimularityCompare_92C(pAdapter, result, c1, c2);
}
VOID
// Save ADDA parameters, turn Path A ADDA on
phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92D, pHalData->IQK_BB_backup, IQK_BB_REG_NUM_92D);
- else
- phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
+ phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
}
phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
-
-
- if(IS_HARDWARE_TYPE_8192D(pAdapter)){
- //==============================
- //3 Path Diversity
- ////Neil Chen--2011--05--20
- rfPathSwitch =(u1Byte) (PHY_QueryBBReg(pAdapter, 0xB30, bMaskDWord)>>27);
- //rfPathSwitch = (u1Byte) DataB30;
- rfPathSwitch = rfPathSwitch&(0x01);
-
- if(rfPathSwitch) // Path Div On
- {
- phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
- //DbgPrint("=STEP= change ADDA Path from B to A Path\n");
- }
- else
- {
- phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
- }
- //3 end
- //=====================================
-
- PHY_SetBBReg(pAdapter, rPdp_AntA, bMaskDWord, 0x01017038);
- }
-
if(t==0)
- {
pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8));
- }
if(!pHalData->bRfPiEnable){
// Switch BB to PI mode to do IQ Calibration.
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xf00000, 0x0f);
- else
- {
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
- }
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
- if(is2T)
- {
+ if(is2T) {
PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
}
//MAC settings
phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- {
- PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x0f600000);
-
- if(is2T)
- {
- PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x0f600000);
- }
- }
- else
- {
- //Page B init
- PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
+ //Page B init
+ PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
- if(is2T)
- {
- PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
- }
- }
+ if(is2T)
+ PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
// IQ calibration setting
RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
IN bool is2T
)
{
- if(IS_HARDWARE_TYPE_8192D(pAdapter))
- {
-#if SWLCK == 1
- phy_LCCalibrate92DSW(pAdapter, is2T);
-#else
- phy_LCCalibrate92D(pAdapter, is2T);
-#endif
- }
- else
- {
- phy_LCCalibrate92C(pAdapter, is2T);
- }
+ phy_LCCalibrate92C(pAdapter, is2T);
}
}
}
- if(IS_HARDWARE_TYPE_8192D(pAdapter) && final_candidate != 0xFF)
- {
- Indexforchannel = GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
-
- for(i = 0; i < IQK_Matrix_REG_NUM; i++)
- pHalData->IQKMatrixRegSetting[Indexforchannel].Value[0][i] =
- result[final_candidate][i];
-
- pHalData->IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;
-
- RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
- }
-
- if(!IS_HARDWARE_TYPE_8192D(pAdapter))
- phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9);
+ phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9);
}
//default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
return;
-
-#if DISABLE_BB_RF
- return;
-#endif
-
- if(IS_HARDWARE_TYPE_8192D(pAdapter) || IS_HARDWARE_TYPE_8723A(pAdapter))
- return;
-
-#if FOR_BRAZIL_PRETEST != 1
- if(pHalData->bAPKdone)
-#endif
- return;
-
- if(IS_92C_SERIAL( pHalData->VersionID)){
- phy_APCalibrate_8192C(pAdapter, delta, TRUE);
- }
- else{
- // For 88C 1T1R
- phy_APCalibrate_8192C(pAdapter, delta, FALSE);
- }
}
phy_InitBBRFRegisterDefinition(Adapter);
- if(IS_HARDWARE_TYPE_8723A(Adapter))
- {
- // Suggested by Scott. tynli_test. 2010.12.30.
- //1. 0x28[1] = 1
- TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
- rtw_udelay_os(2);
- rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
- rtw_udelay_os(2);
-
- //2. 0x29[7:0] = 0xFF
- rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
- rtw_udelay_os(2);
-
- //3. 0x02[1:0] = 2b'11
- TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
- rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
+ // Suggested by Scott. tynli_test. 2010.12.30.
+ //1. 0x28[1] = 1
+ TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
+ rtw_udelay_os(2);
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
+ rtw_udelay_os(2);
- //4. 0x25[6] = 0
- TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
+ //2. 0x29[7:0] = 0xFF
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
+ rtw_udelay_os(2);
- //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09.
- TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
-
- //6. 0x1f[7:0] = 0x07
- rtw_write8(Adapter, REG_RF_CTRL, 0x07);
- }
- else
- {
- // Enable BB and RF
- RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
- rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
-
- // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
- rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
- rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
-
- rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
-
-#ifdef CONFIG_USB_HCI
- rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
-#else
- rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
-#endif
+ //3. 0x02[1:0] = 2b'11
+ TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
+ rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
- // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1.
-#ifdef CONFIG_USB_HCI
- //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
- rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
- rtw_write8(Adapter, 0x15, 0xe9);
-#endif
+ //4. 0x25[6] = 0
+ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
+ //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09.
+ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
-#ifdef CONFIG_PCI_HCI
- // Force use left antenna by default for 88C.
- // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
- if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
- {
- RegVal = rtw_read32(Adapter, REG_LEDCFG0);
- rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
- }
-#endif
- }
+ //6. 0x1f[7:0] = 0x07
+ rtw_write8(Adapter, REG_RF_CTRL, 0x07);
//
// Config BB and AGC
//
rtStatus = phy_BB8723a_Config_ParaFile(Adapter);
-#ifdef CONFIG_USB_HCI
- if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)
- &&(pHalData->BoardType == BOARD_USB_High_PA))
- rtw_write8(Adapter, 0xc72, 0x50);
-#endif
//only for B-cut
- if(IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01)
- {
+ if(pHalData->EEPROMVersion >= 0x01) {
CrystalCap = pHalData->CrystalCap & 0x3F;
PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
}
- if(IS_HARDWARE_TYPE_8723AE(Adapter))
- PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
+ PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
return rtStatus;
}
{
if(Rtl819XRadioB_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
-#if 0//#ifdef CONFIG_USB_HCI
- #ifdef CONFIG_LONG_DELAY_ISSUE
- rtw_msleep_os(1000);
- #else
- rtw_mdelay_os(1000);
- #endif
-#else
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
-#endif
}
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
rtw_mdelay_os(5);
if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
-
- #if 0
- //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
- #else
_PHY_SwChnl8192C(Adapter, channel);
- #endif
if(bResult)
{
}
else
{
- //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
- //if(IS_HARDWARE_TYPE_8192SU(Adapter))
- //{
- // pHalData->SwChnlInProgress = FALSE;
- pHalData->CurrentChannel = tmpchannel;
- //}
+ pHalData->CurrentChannel = tmpchannel;
}
- }
- else
- {
- //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
- //if(IS_HARDWARE_TYPE_8192SU(Adapter))
- //{
- // pHalData->SwChnlInProgress = FALSE;
- pHalData->CurrentChannel = tmpchannel;
- //}
+ } else {
+ pHalData->CurrentChannel = tmpchannel;
}
}
OUT u32 *delay
)
{
-#if 0
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
- SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
- u4Byte PreCommonCmdCnt;
- SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
- u4Byte PostCommonCmdCnt;
- SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
- u4Byte RfDependCmdCnt;
- SwChnlCmd *CurrentCmd;
- u1Byte eRFPath;
- u4Byte RfTXPowerCtrl;
- bool bAdjRfTXPowerCtrl = _FALSE;
-
-
- RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
- RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
- RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
-
- pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
- RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
-
- //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
- //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
- //{
- // <1> Fill up pre common command.
- PreCommonCmdCnt = 0;
- phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
- CmdID_SetTxPowerLevel, 0, 0, 0);
- phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
- CmdID_End, 0, 0, 0);
-
- // <2> Fill up post common command.
- PostCommonCmdCnt = 0;
-
- phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
- CmdID_End, 0, 0, 0);
-
- // <3> Fill up RF dependent command.
- RfDependCmdCnt = 0;
- switch( pHalData->RFChipID )
- {
- case RF_8225:
- RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
- // 2008/09/04 MH Change channel.
- if(channel==14) channel++;
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_End, 0, 0, 0);
- break;
-
- case RF_8256:
- // TEST!! This is not the table for 8256!!
- RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_RF_WriteReg, rRfChannel, channel, 10);
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_End, 0, 0, 0);
- break;
-
- case RF_6052:
- RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
- phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_End, 0, 0, 0);
-
- break;
-
- case RF_8258:
- break;
-
- // For FPGA two MAC verification
- case RF_PSEUDO_11N:
- return TRUE;
- default:
- RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
- return FALSE;
- break;
- }
-
-
- do{
- switch(*stage)
- {
- case 0:
- CurrentCmd=&PreCommonCmd[*step];
- break;
- case 1:
- CurrentCmd=&RfDependCmd[*step];
- break;
- case 2:
- CurrentCmd=&PostCommonCmd[*step];
- break;
- }
-
- if(CurrentCmd->CmdID==CmdID_End)
- {
- if((*stage)==2)
- {
- return TRUE;
- }
- else
- {
- (*stage)++;
- (*step)=0;
- continue;
- }
- }
-
- switch(CurrentCmd->CmdID)
- {
- case CmdID_SetTxPowerLevel:
- PHY_SetTxPowerLevel8192C(Adapter,channel);
- break;
- case CmdID_WritePortUlong:
- PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
- break;
- case CmdID_WritePortUshort:
- PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
- break;
- case CmdID_WritePortUchar:
- PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
- break;
- case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
- for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
- {
-#if 1
- pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
- PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
-#else
- PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
-#endif
- }
- break;
- }
-
- break;
- }while(TRUE);
- //cosa }/*for(Number of RF paths)*/
-
- (*delay)=CurrentCmd->msDelay;
- (*step)++;
- return FALSE;
-#endif
return _TRUE;
}
("%s: MAC has already power on\n", __FUNCTION__));
}
-#if 0
- if(bSupportRemoteWakeUp && Adapter->bWakeFromPnpSleep && pHalData->bMACFuncEnable)
- {
- if(IS_HARDWARE_TYPE_8723AU(Adapter))
- {
- FW_CTRL_PS_MODE FwPwrMode = FW_PS_ACTIVE_MODE;
-
- pHalData->H2CStopInsertQueue = FALSE;
-
- if(pMgntInfo->mAssoc &&
- pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
- (pMgntInfo->PowerSaveControl.WoWLANLPSLevel > 0))
- {
- RT_TRACE(COMP_POWER, DBG_LOUD, ("FwLPS: Active!!\n"));
- rtw_hal_set_hwreg(Adapter, HW_VAR_H2C_FW_PWRMODE, (pu1Byte)(&FwPwrMode));
- }
-
- HalSetFWWoWlanMode92C(Adapter, FALSE);
-
- // Clear WoWLAN event FTISR[WWLAN_INT_EN].
- if(IS_FW_8723A(Adapter) && Adapter->MgntInfo.FirmwareVersion < 10)
- {
- // Fw revises the bug after version 10.
- value8 = rtw_read8(Adapter, REG_FTISR+3);
- rtw_write8(Adapter, REG_FTISR+3, value8|BIT2);
- }
-
- SimpleInitializeAdapter8192CUsb(Adapter);
-
- pMgntInfo->init_adpt_in_progress = FALSE;
- return RT_STATUS_SUCCESS;
- }
- }
-#endif
-
-
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = _InitPowerOn(Adapter);
if(status == _FAIL){
DBG_8723A("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
(pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
- //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
-
- //if(IS_HARDWARE_TYPE_8723A(Adapter))
- // readAdapterInfo_8723U(Adapter);
- //else
- readAdapterInfo(Adapter);
+ readAdapterInfo(Adapter);
}
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
pHalData->SlimComboDbg = _FALSE; // Default is not debug mode.
-
- // 2010/11/22 MH We need to enter debug mode for TSMA and UMC A cut
- //if ((Adapter->chip_type == RTL8188C_8192C) &&
-/*
- if (IS_HARDWARE_TYPE_8192CU(Adapter) &&
- (pHalData->BoardType == BOARD_USB_COMBO))
- {
- switch (pHalData->VersionID)
- {
- case VERSION_NORMAL_TSMC_CHIP_88C:
- case VERSION_NORMAL_TSMC_CHIP_92C:
- case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
- case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
- case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
- case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
- if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
- pHalData->SlimComboDbg = _TRUE;
-
- break;
-
- case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
- case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
- case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
- // 2011/02/15 MH UNC-B cut ECO fail, we need to support slim combo debug mode.
- if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20)
- pHalData->SlimComboDbg = _TRUE;
- break;
-
- default:
- break;
- }
-
- }
-*/
}
//
OSDN Git Service
