EESR_TDE,
.fdr_value = 0x0000070f,
- .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
+ .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
.no_psr = 1,
.apr = 1,
EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
.fdr_value = 0x00000f0f,
- .trscer_err_mask = DESC_I_RINT8,
+ .trscer_err_mask = TRSCER_RMAFCE,
.apr = 1,
.mpr = 1,
.fdr_value = 0x0000070f,
- .trscer_err_mask = DESC_I_RINT8 | DESC_I_RINT5,
+ .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
.apr = 1,
.mpr = 1,
EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
EESIPR_PREIP | EESIPR_CERFIP,
- .trscer_err_mask = DESC_I_RINT8,
+ .trscer_err_mask = TRSCER_RMAFCE,
.tsu = 1,
.dual_port = 1,
};
/* TRSCER */
-enum DESC_I_BIT {
- DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
- DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
- DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
- DESC_I_RINT1 = 0x0001,
-};
-
-#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
+enum TRSCER_BIT {
+ TRSCER_CNDCE = 0x00000800,
+ TRSCER_DLCCE = 0x00000400,
+ TRSCER_CDCE = 0x00000200,
+ TRSCER_TROCE = 0x00000100,
+ TRSCER_RMAFCE = 0x00000080,
+ TRSCER_RRFCE = 0x00000010,
+ TRSCER_RTLFCE = 0x00000008,
+ TRSCER_RTSFCE = 0x00000004,
+ TRSCER_PRECE = 0x00000002,
+ TRSCER_CERFCE = 0x00000001,
+};
+
+#define DEFAULT_TRSCER_ERR_MASK (TRSCER_RMAFCE | TRSCER_RRFCE | TRSCER_CDCE)
/* RPADIR */
enum RPADIR_BIT {