Summary: Implementations based on ISD::SELECT.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315153
91177308-0d34-0410-b5e6-
96231b3b80d8
Known.Zero.setBitsFrom(InBitWidth);
break;
}
+ case X86ISD::CMOV: {
+ DAG.computeKnownBits(Op.getOperand(1), Known, Depth+1);
+ // If we don't know any bits, early out.
+ if (Known.isUnknown())
+ break;
+ KnownBits Known2;
+ DAG.computeKnownBits(Op.getOperand(0), Known2, Depth+1);
+
+ // Only known if known in both the LHS and RHS.
+ Known.One &= Known2.One;
+ Known.Zero &= Known2.Zero;
+ break;
+ }
}
}
case X86ISD::VPCOMU:
// Vector compares return zero/all-bits result values.
return VTBits;
+
+ case X86ISD::CMOV: {
+ unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth+1);
+ if (Tmp0 == 1) return 1; // Early out.
+ unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth+1);
+ return std::min(Tmp0, Tmp1);
+ }
}
// Fallback case.
; NOCMOV-NEXT: leal 12(%esp), %ecx
; NOCMOV-NEXT: [[TBB]]:
; NOCMOV-NEXT: movl (%ecx), %eax
-; NOCMOV-NEXT: orl $4, %ecx
-; NOCMOV-NEXT: movl (%ecx), %edx
+; NOCMOV-NEXT: movl 4(%ecx), %edx
; NOCMOV-NEXT: retl
define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
entry:
; NOCMOV-NEXT: leal 20(%esp), %ecx
; NOCMOV-NEXT: [[TBB]]:
; NOCMOV-NEXT: movl (%ecx), %eax
-; NOCMOV-NEXT: orl $4, %ecx
-; NOCMOV-NEXT: movl (%ecx), %edx
+; NOCMOV-NEXT: movl 4(%ecx), %edx
; NOCMOV-NEXT: retl
define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
entry:
; X86-NEXT: cmovnel %ecx, %edx
; X86-NEXT: cmovnel %eax, %ecx
; X86-NEXT: andl $-2, %edx
-; X86-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-NEXT: addl $7, %edx
; X86-NEXT: adcxl %eax, %ecx
; X86-NEXT: pushl %ecx