{BFD_RELOC_CRX_NUM16, R_CRX_NUM16},
{BFD_RELOC_CRX_NUM32, R_CRX_NUM32},
{BFD_RELOC_CRX_IMM16, R_CRX_IMM16},
- {BFD_RELOC_CRX_IMM32, R_CRX_IMM32}
+ {BFD_RELOC_CRX_IMM32, R_CRX_IMM32},
+ {BFD_RELOC_CRX_SWITCH8, R_CRX_SWITCH8},
+ {BFD_RELOC_CRX_SWITCH16, R_CRX_SWITCH16},
+ {BFD_RELOC_CRX_SWITCH32, R_CRX_SWITCH32}
};
static reloc_howto_type crx_elf_howto_table[] =
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
- FALSE) /* pcrel_offset */
+ FALSE), /* pcrel_offset */
+
+ /* An 8 bit switch table entry. This is generated for an expression
+ such as ``.byte L1 - L2''. The offset holds the difference
+ between the reloc address and L2. */
+ HOWTO (R_CRX_SWITCH8, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_CRX_SWITCH8", /* name */
+ FALSE, /* partial_inplace */
+ 0xff, /* src_mask */
+ 0xff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* A 16 bit switch table entry. This is generated for an expression
+ such as ``.word L1 - L2''. The offset holds the difference
+ between the reloc address and L2. */
+ HOWTO (R_CRX_SWITCH16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_CRX_SWITCH16", /* name */
+ FALSE, /* partial_inplace */
+ 0xffff, /* src_mask */
+ 0xffff, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* A 32 bit switch table entry. This is generated for an expression
+ such as ``.long L1 - L2''. The offset holds the difference
+ between the reloc address and L2. */
+ HOWTO (R_CRX_SWITCH32, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_CRX_SWITCH32", /* name */
+ FALSE, /* partial_inplace */
+ 0xffffffff, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ TRUE) /* pcrel_offset */
};
/* Retrieve a howto ptr using a BFD reloc_code. */
return bfd_reloc_ok;
break;
+ case R_CRX_SWITCH8:
+ case R_CRX_SWITCH16:
+ case R_CRX_SWITCH32:
+ /* We only care about the addend, where the difference between
+ expressions is kept. */
+ Rvalue = 0;
+
default:
break;
}
Rvalue |= (((bfd_get_16 (input_bfd, hit_data) << 16) |
bfd_get_16 (input_bfd, hit_data + 2)) & ~howto->dst_mask);
- if (r_type == R_CRX_NUM32)
+ if (r_type == R_CRX_NUM32 || r_type == R_CRX_SWITCH32)
/* Relocation on DATA is purely little-endian, that is, for a
multi-byte datum, the lowest address in memory contains the
little end of the datum, that is, the least significant byte.
if (isym->st_shndx == sec_shndx
&& isym->st_value > addr
&& isym->st_value < toaddr)
- isym->st_value -= count;
+ {
+ /* Adjust the addend of SWITCH relocations in this section,
+ which reference this local symbol. */
+ for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
+ {
+ unsigned long r_symndx;
+ Elf_Internal_Sym *rsym;
+ bfd_vma addsym, subsym;
+
+ /* Skip if not a SWITCH relocation. */
+ if (ELF32_R_TYPE (irel->r_info) != (int) R_CRX_SWITCH8
+ && ELF32_R_TYPE (irel->r_info) != (int) R_CRX_SWITCH16
+ && ELF32_R_TYPE (irel->r_info) != (int) R_CRX_SWITCH32)
+ continue;
+
+ r_symndx = ELF32_R_SYM (irel->r_info);
+ rsym = (Elf_Internal_Sym *) symtab_hdr->contents + r_symndx;
+
+ /* Skip if not the local adjusted symbol. */
+ if (rsym != isym)
+ continue;
+
+ addsym = isym->st_value;
+ subsym = addsym - irel->r_addend;
+
+ /* Fix the addend only when -->> (addsym > addr >= subsym). */
+ if (subsym <= addr)
+ irel->r_addend -= count;
+ else
+ continue;
+ }
+
+ isym->st_value -= count;
+ }
}
/* Now adjust the global symbols defined in this section. */
/* opc12 r rbase ridx scl2 disps22 */ \
{NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, {{rbase_ridx_scl2_dispu22,0}, {regr,16}}}
- LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4),
+ LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4),
LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4),
LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4),
CSTBIT_INST ("cbitw", i4, 0x382, 0x10, 20, 0xBD),
CSTBIT_INST ("cbitd", i5, 0x1C3, 0x8, 21, 0x7B),
{"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
- {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
+ {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
CSTBIT_INST ("sbitb", i3, 0x701, 0x20, 19, 0x1FD),
CSTBIT_INST ("sbitw", i4, 0x383, 0x10, 20, 0xBE),
CSTBIT_INST ("sbitd", i5, 0x1C4, 0x8, 21, 0x7C),
{"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
- {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
+ {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
CSTBIT_INST ("tbitb", i3, 0x702, 0x20, 19, 0x1FE),
CSTBIT_INST ("tbitw", i4, 0x384, 0x10, 20, 0xBF),
CSTBIT_INST ("tbitd", i5, 0x1C5, 0x8, 21, 0x7D),
{"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
- {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
+ {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
/* Instructions including a register list (opcode is represented as a mask). */
#define REGLIST_INST(NAME, OPC) \
/* opc12 r mask16 */ \
{NAME, 2, OPC, 20, REG_LIST, {{regr,16}, {i16,0}}}
- REG1_INST ("getrfid", 0xFF9),
- REG1_INST ("setrfid", 0xFFA),
+ REG1_INST ("getrfid", 0xFF9),
+ REG1_INST ("setrfid", 0xFFA),
REGLIST_INST ("push", 0x346),
REG1_INST ("push", 0xFFB),
+ REGLIST_INST ("pushx", 0x347),
REGLIST_INST ("pop", 0x324),
REG1_INST ("pop", 0xFFC),
+ REGLIST_INST ("popx", 0x327),
REGLIST_INST ("popret", 0x326),
REG1_INST ("popret", 0xFFD),
- REGLIST_INST ("loadm", 0x324),
+ REGLIST_INST ("loadm", 0x324),
REGLIST_INST ("loadma", 0x325),
- REGLIST_INST ("popma", 0x325),
+ REGLIST_INST ("popma", 0x325),
- REGLIST_INST ("storm", 0x344),
+ REGLIST_INST ("storm", 0x344),
REGLIST_INST ("storma", 0x345),
REGLIST_INST ("pushma", 0x345),
REG(ra, 0xe, CRX_R_REGTYPE),
REG(sp, 0xf, CRX_R_REGTYPE),
-/* Build a user register ur<N>. */
+/* Build a user register u<N>. */
#define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
REG_U(0), REG_U(1), REG_U(2), REG_U(3),
REG_C(8), REG_C(9), REG_C(10), REG_C(11),
REG_C(12), REG_C(13), REG_C(14), REG_C(15),
-/* Build a Coprocessor Special register c<N>. */
+/* Build a Coprocessor Special register cs<N>. */
#define REG_CS(N) REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)
REG_CS(0), REG_CS(1), REG_CS(2), REG_CS(3),
OSDN Git Service
