#define TJA1120_VEND1_EXT_TS_MODE 0x1012
+#define TJA1120_EGRESS_TS_DATA_S 0x9060
+#define TJA1120_EGRESS_TS_END 0x9067
+#define TJA1120_TS_VALID BIT(0)
+#define TJA1120_MORE_TS BIT(15)
+
#define VEND1_PHY_IRQ_ACK 0x80A0
#define VEND1_PHY_IRQ_EN 0x80A1
#define VEND1_PHY_IRQ_STATUS 0x80A2
#define VEND1_PORT_ABILITIES 0x8046
#define PTP_ABILITY BIT(3)
+#define VEND1_PORT_FUNC_IRQ_EN 0x807A
+#define PTP_IRQS BIT(3)
+
+#define VEND1_PTP_IRQ_ACK 0x9008
+#define EGR_TS_IRQ BIT(1)
+
#define VEND1_PORT_INFRA_CONTROL 0xAC00
#define PORT_INFRA_CONTROL_EN BIT(14)
#define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb)
+struct nxp_c45_phy;
+
struct nxp_c45_skb_cb {
struct ptp_header *header;
unsigned int type;
int n_stats;
u8 ptp_clk_period;
bool ext_ts_both_edges;
+ bool ack_ptp_irq;
void (*counters_enable)(struct phy_device *phydev);
+ bool (*get_egressts)(struct nxp_c45_phy *priv,
+ struct nxp_c45_hwts *hwts);
void (*ptp_init)(struct phy_device *phydev);
void (*ptp_enable)(struct phy_device *phydev, bool enable);
};
regmap->vend1_ext_trg_ctrl, RING_DONE);
}
-static bool nxp_c45_get_hwtxts(struct nxp_c45_phy *priv,
- struct nxp_c45_hwts *hwts)
+static void nxp_c45_read_egress_ts(struct nxp_c45_phy *priv,
+ struct nxp_c45_hwts *hwts)
{
const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
struct phy_device *phydev = priv->phydev;
- bool valid;
- u16 reg;
-
- mutex_lock(&priv->ptp_lock);
- phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL,
- RING_DONE);
- reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0);
- valid = !!(reg & RING_DATA_0_TS_VALID);
- if (!valid)
- goto nxp_c45_get_hwtxts_out;
hwts->domain_number =
nxp_c45_read_reg_field(phydev, ®map->domain_number);
nxp_c45_read_reg_field(phydev, ®map->nsec_29_16) << 16;
hwts->sec = nxp_c45_read_reg_field(phydev, ®map->sec_1_0);
hwts->sec |= nxp_c45_read_reg_field(phydev, ®map->sec_4_2) << 2;
+}
+
+static bool nxp_c45_get_hwtxts(struct nxp_c45_phy *priv,
+ struct nxp_c45_hwts *hwts)
+{
+ bool valid;
+ u16 reg;
+ mutex_lock(&priv->ptp_lock);
+ phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL,
+ RING_DONE);
+ reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0);
+ valid = !!(reg & RING_DATA_0_TS_VALID);
+ if (!valid)
+ goto nxp_c45_get_hwtxts_out;
+
+ nxp_c45_read_egress_ts(priv, hwts);
nxp_c45_get_hwtxts_out:
mutex_unlock(&priv->ptp_lock);
return valid;
}
+static bool tja1120_egress_ts_is_valid(struct phy_device *phydev)
+{
+ bool valid;
+ u16 reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S);
+ valid = !!(reg & TJA1120_TS_VALID);
+
+ return valid;
+}
+
+static bool tja1120_get_hwtxts(struct nxp_c45_phy *priv,
+ struct nxp_c45_hwts *hwts)
+{
+ struct phy_device *phydev = priv->phydev;
+ bool more_ts;
+ bool valid;
+ u16 reg;
+
+ mutex_lock(&priv->ptp_lock);
+ reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END);
+ more_ts = !!(reg & TJA1120_MORE_TS);
+ valid = tja1120_egress_ts_is_valid(phydev);
+ if (!valid) {
+ if (!more_ts)
+ goto tja1120_get_hwtxts_out;
+
+ /* Bug workaround for TJA1120 engineering samples: move the
+ * new timestamp from the FIFO to the buffer.
+ */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ TJA1120_EGRESS_TS_END, TJA1120_TS_VALID);
+ valid = tja1120_egress_ts_is_valid(phydev);
+ if (!valid)
+ goto tja1120_get_hwtxts_out;
+ }
+ nxp_c45_read_egress_ts(priv, hwts);
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S,
+ TJA1120_TS_VALID);
+tja1120_get_hwtxts_out:
+ mutex_unlock(&priv->ptp_lock);
+ return valid;
+}
+
static void nxp_c45_process_txts(struct nxp_c45_phy *priv,
struct nxp_c45_hwts *txts)
{
static long nxp_c45_do_aux_work(struct ptp_clock_info *ptp)
{
struct nxp_c45_phy *priv = container_of(ptp, struct nxp_c45_phy, caps);
+ const struct nxp_c45_phy_data *data = nxp_c45_get_data(priv->phydev);
bool poll_txts = nxp_c45_poll_txts(priv->phydev);
struct skb_shared_hwtstamps *shhwtstamps_rx;
struct ptp_clock_event event;
u32 ts_raw;
while (!skb_queue_empty_lockless(&priv->tx_queue) && poll_txts) {
- txts_valid = nxp_c45_get_hwtxts(priv, &hwts);
+ txts_valid = data->get_egressts(priv, &hwts);
if (unlikely(!txts_valid)) {
/* Still more skbs in the queue */
reschedule = true;
ret = IRQ_HANDLED;
}
- /* There is no need for ACK.
- * The irq signal will be asserted until the EGR TS FIFO will be
- * emptied.
- */
irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status);
if (irq) {
- while (nxp_c45_get_hwtxts(priv, &hwts))
+ /* If ack_ptp_irq is false, the IRQ bit is self-clear and will
+ * be cleared when the EGR TS FIFO is empty. Otherwise, the
+ * IRQ bit should be cleared before reading the timestamp,
+ */
+ if (data->ack_ptp_irq)
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ VEND1_PTP_IRQ_ACK, EGR_TS_IRQ);
+ while (data->get_egressts(priv, &hwts))
nxp_c45_process_txts(priv, &hwts);
ret = IRQ_HANDLED;
.n_stats = ARRAY_SIZE(tja1103_hw_stats),
.ptp_clk_period = PTP_CLK_PERIOD_100BT1,
.ext_ts_both_edges = false,
+ .ack_ptp_irq = false,
.counters_enable = tja1103_counters_enable,
+ .get_egressts = nxp_c45_get_hwtxts,
.ptp_init = tja1103_ptp_init,
.ptp_enable = tja1103_ptp_enable,
};
.n_stats = ARRAY_SIZE(tja1120_hw_stats),
.ptp_clk_period = PTP_CLK_PERIOD_1000BT1,
.ext_ts_both_edges = true,
+ .ack_ptp_irq = true,
.counters_enable = tja1120_counters_enable,
+ .get_egressts = tja1120_get_hwtxts,
.ptp_init = tja1120_ptp_init,
.ptp_enable = tja1120_ptp_enable,
};