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dt-bindings: mmc: sdhci-of-arasan: Add new compatible for Intel LGM SDXC
authorRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Wed, 9 Oct 2019 01:28:17 +0000 (09:28 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Wed, 13 Nov 2019 15:10:16 +0000 (16:10 +0100)
Add a new compatible to use the sdhc-arasan host controller driver
with the SDXC PHY to support on Intel's Lightning Mountain(LGM) SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

index 7ca0aa7..eb78d9a 100644 (file)
@@ -19,6 +19,8 @@ Required Properties:
        Note: This binding has been deprecated and moved to [5].
     - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+    - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
+      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
 
   [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
 
@@ -97,3 +99,18 @@ Example:
                phy-names = "phy_arasan";
                arasan,soc-ctl-syscon = <&sysconf>;
        };
+
+       sdxc: sdhci@ec600000 {
+               compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
+               reg = <0xec600000 0x300>;
+               interrupt-parent = <&ioapic1>;
+               interrupts = <43 1>;
+               clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
+                        <&cgu0 LGM_GCLK_SDXC>;
+               clock-names = "clk_xin", "clk_ahb", "gate";
+               clock-output-names = "sdxc_cardclock";
+               #clock-cells = <0>;
+               phys = <&sdxc_phy>;
+               phy-names = "phy_arasan";
+               arasan,soc-ctl-syscon = <&sysconf>;
+       };