arm64: dts: qcom: sa8775p: add UFS nodes

Add nodes for the UFS and its PHY on sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411130446.401440-5-brgl@bgdev.pl

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 3f3e584..8a0e53f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -590,6 +590,64 @@
                        };
                };
 
+               ufs_mem_hc: ufs@1d84000 {
+                       compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+                       reg = <0x0 0x01d84000 0x0 0x3000>;
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufs_mem_phy>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <2>;
+                       #reset-cells = <1>;
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+                       iommus = <&apps_smmu 0x100 0x0>;
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk",
+                                     "rx_lane1_sync_clk";
+                       freq-table-hz = <75000000 300000000>,
+                                       <0 0>,
+                                       <0 0>,
+                                       <75000000 300000000>,
+                                       <0 0>,
+                                       <0 0>,
+                                       <0 0>,
+                                       <0 0>;
+                       status = "disabled";
+               };
+
+               ufs_mem_phy: phy@1d87000 {
+                       compatible = "qcom,sa8775p-qmp-ufs-phy";
+                       reg = <0x0 0x01d87000 0x0 0xe10>;
+                       /*
+                        * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
+                        * enables the CXO clock to eDP *and* UFS PHY.
+                        */
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&gcc GCC_EDP_REF_CLKREF_EN>;
+                       clock-names = "ref", "ref_aux", "qref";
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x20000>;