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Mention missing CPU save/restore.
author
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Wed, 7 May 2008 15:39:12 +0000
(15:39 +0000)
committer
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Wed, 7 May 2008 15:39:12 +0000
(15:39 +0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381
c046a42c
-6fe2-441c-8c8c-
71466251a162
target-mips/TODO
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diff --git
a/target-mips/TODO
b/target-mips/TODO
index
dda5801
..
c58956c
100644
(file)
--- a/
target-mips/TODO
+++ b/
target-mips/TODO
@@
-29,6
+29,7
@@
General
To cope with these differences, Qemu currently flushes the TLB at
each ASID change. Using the MMU modes to implement ASIDs hinges on
implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
MIPS64
------