OSDN Git Service

arm64: dts: add LS1043A DPAA FMan support
authorMadalin Bucur <madalin.bucur@nxp.com>
Tue, 16 May 2017 12:07:22 +0000 (15:07 +0300)
committerShawn Guo <shawnguo@kernel.org>
Sun, 21 May 2017 02:13:47 +0000 (10:13 +0800)
Add the DPAA 1.x FMan device tree nodes for LS1043A boards.

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
new file mode 100644 (file)
index 0000000..169e171
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * QorIQ FMan v3 device tree nodes for ls1043
+ *
+ * Copyright 2015-2016 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+ */
+
+&soc {
+
+/* include used FMan blocks */
+#include "qoriq-fman3-0.dtsi"
+#include "qoriq-fman3-0-1g-0.dtsi"
+#include "qoriq-fman3-0-1g-1.dtsi"
+#include "qoriq-fman3-0-1g-2.dtsi"
+#include "qoriq-fman3-0-1g-3.dtsi"
+#include "qoriq-fman3-0-1g-4.dtsi"
+#include "qoriq-fman3-0-1g-5.dtsi"
+#include "qoriq-fman3-0-10g-0.dtsi"
+
+};
+
+&fman0 {
+       /* these aliases provide the FMan ports mapping */
+       enet0: ethernet@e0000 {
+       };
+
+       enet1: ethernet@e2000 {
+       };
+
+       enet2: ethernet@e4000 {
+       };
+
+       enet3: ethernet@e6000 {
+       };
+
+       enet4: ethernet@e8000 {
+       };
+
+       enet5: ethernet@ea000 {
+       };
+
+       enet6: ethernet@f0000 {
+       };
+};
index a5f1306..6341281 100644 (file)
                reg = <0>;
        };
 };
+
+#include "fsl-ls1043-post.dtsi"
index d64370e..df5b180 100644 (file)
 &duart1 {
        status = "okay";
 };
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+       ethernet@e0000 {
+               phy-handle = <&qsgmii_phy1>;
+               phy-connection-type = "qsgmii";
+       };
+
+       ethernet@e2000 {
+               phy-handle = <&qsgmii_phy2>;
+               phy-connection-type = "qsgmii";
+       };
+
+       ethernet@e4000 {
+               phy-handle = <&rgmii_phy1>;
+               phy-connection-type = "rgmii-txid";
+       };
+
+       ethernet@e6000 {
+               phy-handle = <&rgmii_phy2>;
+               phy-connection-type = "rgmii-txid";
+       };
+
+       ethernet@e8000 {
+               phy-handle = <&qsgmii_phy3>;
+               phy-connection-type = "qsgmii";
+       };
+
+       ethernet@ea000 {
+               phy-handle = <&qsgmii_phy4>;
+               phy-connection-type = "qsgmii";
+       };
+
+       ethernet@f0000 { /* 10GEC1 */
+               phy-handle = <&aqr105_phy>;
+               phy-connection-type = "xgmii";
+       };
+
+       mdio@fc000 {
+               rgmii_phy1: ethernet-phy@1 {
+                       reg = <0x1>;
+               };
+
+               rgmii_phy2: ethernet-phy@2 {
+                       reg = <0x2>;
+               };
+
+               qsgmii_phy1: ethernet-phy@4 {
+                       reg = <0x4>;
+               };
+
+               qsgmii_phy2: ethernet-phy@5 {
+                       reg = <0x5>;
+               };
+
+               qsgmii_phy3: ethernet-phy@6 {
+                       reg = <0x6>;
+               };
+
+               qsgmii_phy4: ethernet-phy@7 {
+                       reg = <0x7>;
+               };
+       };
+
+       mdio@fd000 {
+               aqr105_phy: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       interrupts = <0 132 4>;
+                       reg = <0x1>;
+               };
+       };
+};
index 0e42d20..31fd77f 100644 (file)
        #address-cells = <2>;
        #size-cells = <2>;
 
+       aliases {
+               fman0 = &fman0;
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+               ethernet4 = &enet4;
+               ethernet5 = &enet5;
+               ethernet6 = &enet6;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                interrupts = <1 9 0xf08>;
        };
 
-       soc {
+       soc: soc {
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;