drm/amdgpu: switch hdp callback functions for hdp v5

Switch to use the HDP functions which unified on hdp structure instead of
the scattered hdp callback functions.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index d741fee..e74cd44 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -71,7 +71,7 @@ amdgpu-y += \
        vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
        vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
        arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
-       nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o
+       nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o
 
 # add DF block
 amdgpu-y += \

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ba10867..10aae0a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -38,7 +38,6 @@
 #include "smuio/smuio_11_0_0_offset.h"
 #include "smuio/smuio_11_0_0_sh_mask.h"
 #include "navi10_enum.h"
-#include "hdp/hdp_5_0_0_offset.h"
 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
 
 #include "soc15.h"
@@ -5691,7 +5690,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -5769,7 +5768,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -5846,7 +5845,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6215,7 +6214,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5648c48..3b7c6c3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -27,8 +27,6 @@
 #include "gmc_v10_0.h"
 #include "umc_v8_7.h"
 
-#include "hdp/hdp_5_0_0_offset.h"
-#include "hdp/hdp_5_0_0_sh_mask.h"
 #include "athub/athub_2_0_0_sh_mask.h"
 #include "athub/athub_2_0_0_offset.h"
 #include "dcn/dcn_2_0_0_offset.h"
@@ -312,7 +310,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        int r;
 
        /* flush hdp cache */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       adev->hdp.funcs->flush_hdp(adev, NULL);
 
        /* For SRIOV run time, driver shouldn't access the register through MMIO
         * Directly use kiq to do the vm invalidation instead
@@ -995,7 +993,6 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
 {
        int r;
        bool value;
-       u32 tmp;
 
        if (adev->gart.bo == NULL) {
                dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
@@ -1014,15 +1011,10 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
-       tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
-       WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
-
-       tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
-       WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
+       adev->hdp.funcs->init_registers(adev);
 
        /* Flush HDP after it is initialized */
-       adev->nbio.funcs->hdp_flush(adev, NULL);
+       adev->hdp.funcs->flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 6bee367..1d785f0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -38,8 +38,6 @@
 
 #include "gc/gc_10_1_0_offset.h"
 #include "gc/gc_10_1_0_sh_mask.h"
-#include "hdp/hdp_5_0_0_offset.h"
-#include "hdp/hdp_5_0_0_sh_mask.h"
 #include "smuio/smuio_11_0_0_offset.h"
 #include "mp/mp_11_0_offset.h"
 
@@ -50,6 +48,7 @@
 #include "mmhub_v2_0.h"
 #include "nbio_v2_3.h"
 #include "nbio_v7_2.h"
+#include "hdp_v5_0.h"
 #include "nv.h"
 #include "navi10_ih.h"
 #include "gfx_v10_0.h"
@@ -514,6 +513,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
                adev->nbio.funcs = &nbio_v2_3_funcs;
                adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
        }
+       adev->hdp.funcs = &hdp_v5_0_funcs;
 
        if (adev->asic_type == CHIP_SIENNA_CICHLID)
                adev->gmc.xgmi.supported = true;
@@ -669,22 +669,6 @@ static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
        return adev->nbio.funcs->get_rev_id(adev);
 }
 
-static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
-{
-       adev->nbio.funcs->hdp_flush(adev, ring);
-}
-
-static void nv_invalidate_hdp(struct amdgpu_device *adev,
-                               struct amdgpu_ring *ring)
-{
-       if (!ring || !ring->funcs->emit_wreg) {
-               WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
-       } else {
-               amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
-                                       HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
-       }
-}
-
 static bool nv_need_full_reset(struct amdgpu_device *adev)
 {
        return true;
@@ -788,8 +772,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
        .set_uvd_clocks = &nv_set_uvd_clocks,
        .set_vce_clocks = &nv_set_vce_clocks,
        .get_config_memsize = &nv_get_config_memsize,
-       .flush_hdp = &nv_flush_hdp,
-       .invalidate_hdp = &nv_invalidate_hdp,
        .init_doorbell_index = &nv_init_doorbell_index,
        .need_full_reset = &nv_need_full_reset,
        .need_reset_on_init = &nv_need_reset_on_init,
@@ -1080,120 +1062,6 @@ static int nv_common_soft_reset(void *handle)
        return 0;
 }
 
-static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
-                                          bool enable)
-{
-       uint32_t hdp_clk_cntl, hdp_clk_cntl1;
-       uint32_t hdp_mem_pwr_cntl;
-
-       if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
-                               AMD_CG_SUPPORT_HDP_DS |
-                               AMD_CG_SUPPORT_HDP_SD)))
-               return;
-
-       hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
-       hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
-
-       /* Before doing clock/power mode switch,
-        * forced on IPH & RC clock */
-       hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
-                                    IPH_MEM_CLK_SOFT_OVERRIDE, 1);
-       hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
-                                    RC_MEM_CLK_SOFT_OVERRIDE, 1);
-       WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
-
-       /* HDP 5.0 doesn't support dynamic power mode switch,
-        * disable clock and power gating before any changing */
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        IPH_MEM_POWER_CTRL_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        IPH_MEM_POWER_LS_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        IPH_MEM_POWER_DS_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        IPH_MEM_POWER_SD_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        RC_MEM_POWER_CTRL_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        RC_MEM_POWER_LS_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        RC_MEM_POWER_DS_EN, 0);
-       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                        RC_MEM_POWER_SD_EN, 0);
-       WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
-
-       /* only one clock gating mode (LS/DS/SD) can be enabled */
-       if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_LS_EN, enable);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_LS_EN, enable);
-       } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_DS_EN, enable);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_DS_EN, enable);
-       } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_SD_EN, enable);
-               /* RC should not use shut down mode, fallback to ds */
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_DS_EN, enable);
-       }
-
-       /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
-        * be set for SRAM LS/DS/SD */
-       if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
-                                                       AMD_CG_SUPPORT_HDP_SD)) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                               IPH_MEM_POWER_CTRL_EN, 1);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                               RC_MEM_POWER_CTRL_EN, 1);
-       }
-
-       WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
-
-       /* restore IPH & RC clock override after clock/power mode changing */
-       WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
-}
-
-static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
-                                      bool enable)
-{
-       uint32_t hdp_clk_cntl;
-
-       if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
-               return;
-
-       hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
-
-       if (enable) {
-               hdp_clk_cntl &=
-                       ~(uint32_t)
-                         (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
-                          HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
-                          HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
-                          HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
-                          HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
-                          HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
-       } else {
-               hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
-                       HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
-                       HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
-                       HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
-                       HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
-                       HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
-       }
-
-       WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
-}
-
 static int nv_common_set_clockgating_state(void *handle,
                                           enum amd_clockgating_state state)
 {
@@ -1213,9 +1081,7 @@ static int nv_common_set_clockgating_state(void *handle,
                                state == AMD_CG_STATE_GATE);
                adev->nbio.funcs->update_medium_grain_light_sleep(adev,
                                state == AMD_CG_STATE_GATE);
-               nv_update_hdp_mem_power_gating(adev,
-                                  state == AMD_CG_STATE_GATE);
-               nv_update_hdp_clock_gating(adev,
+               adev->hdp.funcs->update_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                break;
        default:
@@ -1234,31 +1100,13 @@ static int nv_common_set_powergating_state(void *handle,
 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       uint32_t tmp;
 
        if (amdgpu_sriov_vf(adev))
                *flags = 0;
 
        adev->nbio.funcs->get_clockgating_state(adev, flags);
 
-       /* AMD_CG_SUPPORT_HDP_MGCG */
-       tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
-       if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
-                    HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
-                    HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
-                    HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
-                    HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
-                    HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
-               *flags |= AMD_CG_SUPPORT_HDP_MGCG;
-
-       /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
-       tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
-       if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
-               *flags |= AMD_CG_SUPPORT_HDP_LS;
-       else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
-               *flags |= AMD_CG_SUPPORT_HDP_DS;
-       else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
-               *flags |= AMD_CG_SUPPORT_HDP_SD;
+       adev->hdp.funcs->get_clock_gating_state(adev, flags);
 
        return;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index a738a7d..c325d6f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -690,7 +690,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
                }
 
                memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-               adev->nbio.funcs->hdp_flush(adev, NULL);
+               adev->hdp.funcs->flush_hdp(adev, NULL);
                vfree(buf);
        }