indir_n : in std_logic;
indir_x_n : in std_logic;
indir_y_n : in std_logic;
+ ba_out_n : in std_logic;
arith_en_n : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
exec_cycle : in std_logic_vector (5 downto 0);
pcl_inc_n, sp_oe_n, sp_pop_n, sp_push_n,
zp_n, zp_xy_n, abs_xy_n, pg_next_n, rel_calc_n,
int_d_bus(7), indir_n, indir_x_n, exec_cycle,
- indir_y_n
+ indir_y_n, ba_out_n
)
begin
a_sel <= ADDR_INC;
addr1 <= bal;
addr_back <= addr_out;
-
- al_buf_we_n <= '0';
- al_reg_in <= bal;
- if (set_clk = '0') then
- abl <= bal;
- else
- abl <= al_reg;
- end if;
+ abl <= bal;
else
---case push
a_sel <= ADDR_DEC;
addr1 <= bal;
addr_back <= addr_out;
abl <= bal;
-
end if;
elsif (zp_n = '0') then
ea_carry <= '0';
tmp_buf_we_n <= '1';
ea_carry <= '0';
end if; -- if (exec_cycle = T2) then
+ elsif (ba_out_n = '0') then
+ abh <= bah;
+ abl <= bal;
else
al_buf_we_n <= '1';
ah_buf_we_n <= '1';
tmp_buf_we_n <= '1';
ea_carry <= '0';
- abl <= bal;
- abh <= bah;
-
- ----addr_back is always bal for jmp/jsr instruction....
- -----TODO must check later if it's ok.
- addr_back <= bal;
+ abl <= (others => 'Z');
+ abh <= (others => 'Z');
+ addr_back <= (others => 'Z');
end if; --if (pcl_inc_n = '0') then
end process;
indir_n : out std_logic;
indir_x_n : out std_logic;
indir_y_n : out std_logic;
+ ba_out_n : out std_logic;
arith_en_n : out std_logic;
stat_dec_oe_n : out std_logic;
stat_bus_oe_n : out std_logic;
end procedure;
-procedure fetch_inst (inc_pcl : in std_logic) is
+procedure fetch_inst (wk_inc_pcl_n : in std_logic) is
begin
if instruction = conv_std_logic_vector(16#4c#, dsize) then
--if prior cycle is jump instruction,
ad_oe_n <= '0';
pch_cmd <= "1101";
inst_we_n <= '0';
- pcl_inc_n <= inc_pcl;
+ pcl_inc_n <= wk_inc_pcl_n;
+ ba_out_n <= not wk_inc_pcl_n;
r_nw <= '1';
d_print(string'("fetch 1"));
---T0 cycle routine
---(along with the page boundary condition, the last
---cycle is bypassed and slided to T0.)
-procedure t0_cycle(inc_pcl : in std_logic) is
+procedure t0_cycle(wk_inc_pcl_n : in std_logic) is
begin
disable_pins;
if (nmi_n = '0' and nmi_handled_n = '1') then
fetch_inst('1');
wk_next_cycle <= N1;
else
- fetch_inst(inc_pcl);
+ fetch_inst(wk_inc_pcl_n);
wk_next_cycle <= T1;
end if;
end procedure;
pcl_cmd <= "1111";
pch_cmd <= "1111";
r_nw <= 'Z';
+ ba_out_n <= '1';
elsif (exec_cycle = T0r) then
--cycle #1
indir_n <= '1';
indir_x_n <= '1';
indir_y_n <= '1';
+ ba_out_n <= '1';
arith_en_n <= '1';
stat_dec_oe_n <= '0';
n_vec_oe_n <= '0';
wk_next_cycle <= N5;
end if;
+ ba_out_n <= '0';
elsif exec_cycle = R5 or exec_cycle = N5 then
front_we(pcl_cmd, '1');
indir_n : out std_logic;
indir_x_n : out std_logic;
indir_y_n : out std_logic;
+ ba_out_n : out std_logic;\r
arith_en_n : out std_logic;
stat_dec_oe_n : out std_logic;
stat_bus_oe_n : out std_logic;
indir_n : in std_logic;
indir_x_n : in std_logic;
indir_y_n : in std_logic;
+ ba_out_n : in std_logic;\r
arith_en_n : in std_logic;
instruction : in std_logic_vector (dsize - 1 downto 0);
exec_cycle : in std_logic_vector (5 downto 0);
signal indir_n : std_logic;
signal indir_x_n : std_logic;
signal indir_y_n : std_logic;
+ signal ba_out_n : std_logic;\r
signal arith_en_n : std_logic;
signal alu_n : std_logic;
indir_n,
indir_x_n,
indir_y_n,
+ ba_out_n,\r
arith_en_n,
stat_dec_oe_n,
stat_bus_oe_n,
rel_calc_n,
indir_n,
indir_x_n,
- indir_y_n,
+ indir_y_n,\r
+ ba_out_n,
arith_en_n,
instruction,
exec_cycle,
irq_l_buf : tri_state_buffer generic map (dsize)
port map (i_vec_oe_n, irq_l, bal);
irq_h_buf : tri_state_buffer generic map (dsize)
- port map (i_vec_oe_n, irq_h, bah);
-
+ port map (i_vec_oe_n, irq_h, bah);\r
+\r
reset_p : process (rst_n)
begin
if (rst_n = '0') then
OSDN Git Service
