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ASoC: sun4i-i2s: Fix MCLK Enable bit offset on A83t
author
Maxime Ripard
<maxime.ripard@bootlin.com>
Mon, 19 Aug 2019 19:25:22 +0000
(21:25 +0200)
committer
Mark Brown
<broonie@kernel.org>
Tue, 20 Aug 2019 17:33:15 +0000
(18:33 +0100)
The A83t, unlike previous SoCs, has the MCLK enable bit at the 8th bit of
the CLK_DIV register, unlike what is declared in the driver.
Fixes:
21faaea1343f
("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link:
https://lore.kernel.org/r/43b07f8cd8e0e280c64ce61d57c307678c923e9b.1566242458.git-series.maxime.ripard@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sunxi/sun4i-i2s.c
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diff --git
a/sound/soc/sunxi/sun4i-i2s.c
b/sound/soc/sunxi/sun4i-i2s.c
index
59d809d
..
0fce3c4
100644
(file)
--- a/
sound/soc/sunxi/sun4i-i2s.c
+++ b/
sound/soc/sunxi/sun4i-i2s.c
@@
-1047,7
+1047,7
@@
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
- .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG,
7, 7
),
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG,
8, 8
),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.bclk_dividers = sun8i_i2s_clk_div,