libc_common_cflags += -DMALLOC_ALIGNMENT=$(BOARD_MALLOC_ALIGNMENT)
endif
-# Define ANDROID_SMP appropriately.
-ifeq ($(TARGET_CPU_SMP),true)
- libc_common_cflags += -DANDROID_SMP=1
-else
- libc_common_cflags += -DANDROID_SMP=0
-endif
-
# Define some common conlyflags
libc_common_conlyflags := \
-std=gnu99
#define BIONIC_ATOMIC_ARM_H
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
-#if defined(ANDROID_SMP) && ANDROID_SMP == 1
__asm__ __volatile__ ( "dmb ish" : : : "memory" );
-#else
- /* A simple compiler barrier. */
- __asm__ __volatile__ ( "" : : : "memory" );
-#endif
}
/* Compare-and-swap, without any explicit barriers. Note that this function
* on SMP systems emits an appropriate instruction.
*/
-#if !defined(ANDROID_SMP)
-# error "Must define ANDROID_SMP before including atomic-inline.h"
-#endif
-
#ifdef __cplusplus
extern "C" {
#endif
*/
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
-#if defined(ANDROID_SMP) && ANDROID_SMP == 1
__asm__ __volatile__ ( "sync" : : : "memory" );
-#else
- /* A simple compiler barrier. */
- __asm__ __volatile__ ( "" : : : "memory" );
-#endif
}
/* Compare-and-swap, without any explicit barriers. Note that this function
* platform for a multi-core device.
*/
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
-#if defined(ANDROID_SMP) && ANDROID_SMP == 1
__asm__ __volatile__ ( "mfence" : : : "memory" );
-#else
- /* A simple compiler barrier. */
- __asm__ __volatile__ ( "" : : : "memory" );
-#endif
}
/* Compare-and-swap, without any explicit barriers. Note that this function