#define MMU_USER_IDX 3
#define MMU_PHYS_IDX 4
+#define PRIV_TO_MMU_IDX(priv) (priv)
+#define MMU_IDX_TO_PRIV(mmu_idx) (mmu_idx)
+
#define TARGET_INSN_START_EXTRA_WORDS 1
/* Hardware exceptions, interrupts, faults, and traps. */
return MMU_USER_IDX;
#else
if (env->psw & (ifetch ? PSW_C : PSW_D)) {
- return env->iaoq_f & 3;
+ return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
}
return MMU_PHYS_IDX; /* mmu disabled */
#endif
ctx->tb_flags = ctx->base.tb->flags;
#ifdef CONFIG_USER_ONLY
- ctx->privilege = MMU_USER_IDX;
+ ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);
ctx->mmu_idx = MMU_USER_IDX;
- ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
- ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
+ ctx->iaoq_f = ctx->base.pc_first | ctx->privilege;
+ ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege;
ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
- ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
+ ctx->mmu_idx = (ctx->tb_flags & PSW_D ?
+ PRIV_TO_MMU_IDX(ctx->privilege) : MMU_PHYS_IDX);
/* Recover the IAOQ values from the GVA + PRIV. */
uint64_t cs_base = ctx->base.tb->cs_base;